ST72324BJ2 datasheet(14/188 Pages) STMICROELECTRONICS

14 / 188 page

Pin description

ST72324B

14/188

41 34 23 26 OSC2(3)

Resonator oscillator inverter output

42 35 24 27 OSC1(3)

External clock input or Resonator

oscillator inverter input

43 36 25 28 VDD_2

(1)

Digital Main Supply Voltage

44 37 26 29 PE0/TDO

I/O CT

Port E0

SCI Transmit Data Out

38 27 30 PE1/RDI

I/O CT

Port E1

SCI Receive Data In

39 28 31 PB0

I/O CT

Xei2

Port B0

Caution: Negative current

injection not allowed on

this pin(4)

PB1

I/O CT

Xei2

Port B1

PB2

I/O CT

Xei2

Port B2

42 29 32 PB3

I/O CT

Port B3

It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground.

On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after

reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:

Description and Section 12.6: Clock and timing characteristics for more details.

For details refer to Section 12.9.1 on page 153

Table 1.

Device pin description (continued)

Pin No.

Pin Name

Level

Port

Main

function

(after

reset)

Alternate Function

Input

Output

ST72324BJ2 Datasheet(PDF) 14 Page - STMicroelectronics

ST72324BJ2 Datasheet(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL