ST72324BJ2 datasheet(27/188 Pages) STMICROELECTRONICS

27 / 188 page

ST72324B

Supply, reset and clock management

27/188

Figure 12.

Clock, reset and supply block diagram

6.3

Multi-oscillator (MO)

The main clock of the ST7 can be generated by three different source types coming from the

multi-oscillator block:

●

an external source

●

4 crystal or ceramic resonator oscillators

●

an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is

selectable through the option byte. The associated hardware configurations are shown in

Table 8. Refer to the electrical characteristics section for more details.

Caution:

The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left

unconnected, the ST7 main oscillator may start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed maximum (> 16 MHz.), putting the ST7 in an

unsafe/undefined state. The product behavior must therefore be considered undefined when

the OSC pins are left unconnected.

6.3.1

External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle

has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Low Voltage

Detector

(LVD)

fOSC2

Auxiliary Voltage

Detector

(AVD)

Multi-

Oscillator

(MO)

OSC1

RESET

VSS

VDD

Reset Sequence

Manager

(RSM)

OSC2

Main Clock

AVD Interrupt Request

Controller

PLL

System Integrity Management

Watchdog

SICSR

timer (WDG)

with Real-time

Clock (MCC/RTC)

AVD AVD LVD

WDG

fOSC

(option)

fCPU

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