ST72324BJ2 datasheet(106/188 Pages) STMICROELECTRONICS

106 / 188 page

On-chip peripherals

ST72324B

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10.5.4

Functional description

The block diagram of the serial control interface is shown in Figure 57. It contains six

dedicated registers:

●

2 control registers (SCICR1 and SCICR2)

●

a status register (SCISR)

●

a baud rate register (SCIBRR)

●

an extended prescaler receiver register (SCIERPR)

●

an extended prescaler transmitter register (SCIETPR)

Refer to the register descriptions in Section 10.5.7 for the definitions of each bit.

Serial data format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the

SCICR1 register (see Figure 57).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next

frame which contains data.

A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At

the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the

start bit.

Transmission and reception are driven by their own baud rate generator.

Figure 58.

Word length programming

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Start

bit

Stop

bit

Start

bit

Idle frame

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Start

bit

Stop

Bit

Start

bit

Start

bit

Start

bit

9-bit word length (M bit is set)

8-bit word length (M bit is reset)

Possible

Parity

bit

Possible

Parity

bit

Break frame

Start

bit

Extra

’1’

Data frame

Start

bit

Extra

’1’

Data frame

Next data frame

Idle frame

Break frame

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