AS8267 datasheet(106/136 Pages) AMSCO

106 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 106 of 136

Bit

Symbol Function

Not used

WDTE0 Disables and enables the watchdog timer function

0: watchdog disabled

1: watchdog enabled

The watchdog timer has a selectable counter length of 18 bit, 20 bit or 22 bit for the Mclk and 18 bits for the

mcu_clk. It should be noted that while the Mclk has a fixed frequency, depending on the crystal frequency, the

MCU clock is programmable, being divisible by 1 to 128, in binary steps (see MCUCLKDIV Register

(‘mcu_clk’)). The timeout periods below assume the Mclk = 3.579545MHz (fixed crystal frequency).

Watchdog Timer Clock Register (WDTCLK)

MSB

LSB

WDTCLK1

WDTCLK0

Bit

Symbol

Function

Not used

Clock Source

Timeout Period (ms)

Bit1

Bit0

Mclk – default after reset

73.2

WDTCLK1

Mclk

292.8

Mclk

1171.2

Mcu_clk (div=1)

73.2

WDTCLK0

Watchdog timeout period

(Mclk = 3.579545MHz)

Mcuclk (div=128)

9300

nd UART (UART2)

An additional serial interface, UART2 is provided for debugging purposes. UART2 is accessible via two of the

multi-purpose I/Os (MPIO). The UART2 is functionally identical to UART1. The SFR addresses are defined as

follows:

Address

Description

SCON2

C0h

Serial port control register – see Serial Interface – UART1 for details.

SBUF2

C1h

Serial port buffer register – see Serial Interface – UART1 for details.

SBAUDL2

C2h

Baudrate reload register – Low address

SBAUDH2

C3h

Baudrate reload register – High address

SOVR2

B0h

‘Serial overflow’ register, which indicates when data in SBUF has been

overwritten before being read. The flag is the LSB with the other 7 bits all

being 0.

Below is an example how to configure the ports IO7 and IO6 as UART2s txd2 (IO7) and rxd2 (IO6) pins.

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