MPC8280 datasheet(273/1386 Pages) FREESCALE

273 / 1386 page

60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

7-15

7.2.8.1.1

Transfer Acknowledge (TA)—Input

Following are the state meaning and timing comments for the TA input signal.

State Meaning

Asserted—Indicates that a single-beat data transfer completed successfully or that

a data beat in a burst transfer completed successfully. Note that TA must be

asserted for each data beat in a burst transaction. For more information, see

Section 8.5.3, “Data Bus Transfers and Normal Termination.”

Negated—(During assertion of DBB) indicates that, until TA is asserted, the

MPC8280 must continue to drive the data for the current write or must wait to

sample the data for reads.

Timing Comments

Assertion—Depends on whether or not the PCI controller can initiate 60x bus

global transactions when the address retry mechanism is in use:

PCI controller is not used or cannot initiate global transactions— Assertion must

occur at least one cycle following AACK for the current transaction;

otherwise, assertion may occur at any time during the assertion of DBB.

The system can withhold assertion of TA to indicate that the MPC8280

should insert wait states to extend the duration of the data beat.

PCI controller can initiate global transactions—Assertion must occur at least one

clock cycle following AACK for the current transaction and at least one

clock cycle after ARTRY can be asserted.

Negation—Must occur after the bus clock cycle of the final (or only) data beat of

the transfer. For a burst transfer, the system can assert TA for one bus clock cycle

and then negate it to advance the burst transfer to the next beat and insert wait

states during the next beat. (Note: when configured for 1:1 clock mode and is

performing a burst read into the data cache, the MPC8280 requires two wait states

between the assertion of TS and the first assertion of TA for that transaction, or

one wait state for 1.5:1 clock mode.)

7.2.8.1.2

Transfer Acknowledge (TA)—Output

Following are the state meaning and timing comments for TA as an output signal.

State Meaning

Asserted—Indicates that the data has been latched for a write operation, or that the

data is valid for a read operation, thus terminating the current data beat. If it is the

last or only data beat, this also terminates the data tenure.

Negated—Indicates that master must extend the current data beat (insert wait

states) until data can be provided or accepted by the MPC8280.

Timing Comments

Assertion—Depends on whether or not the PCI controller can initiate 60x bus

global transactions when the address retry mechanism is in use:

PCI controller is not used or cannot initiate global transactions—Assertion must

occur at least one cycle following AACK for the current transaction;

occurs on the clock in which the current data transfer can be completed.

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