MPC8280 datasheet(305/1386 Pages) FREESCALE

305 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-29

This sequence is shown in Figure 8-11. In Figure 8-11 the data bus is busy at the beginning of the

transaction, thus delaying the assertion of DBG.

Figure 8-11. Data Tenure Terminated by Assertion of TEA

The MPC8280 interprets the following bus transactions as bus errors:

•

Direct-store transactions, as indicated by the assertion of XATS.

•

Bus errors asserted by slaves (internal or external).

8.6

Memory Coherency—MEI Protocol

The MPC8280 provides dedicated hardware to ensure memory coherency by snooping bus transactions,

by maintaining information about the status of data in a cache block, and by the address retry capability.

Each data cache block includes status bits that support the modified/exclusive/invalid, or MEI,

cache-coherency protocol.

Asserting the global (GBL) output signal indicates whether the current transaction must be snooped by

other snooping devices on the bus. Address bus masters assert GBL to indicate that the current transaction

is a global access (that is, an access to memory shared by more than one device). If GBL is not asserted

for the transaction, that transaction is not snooped. When other devices detect the GBL input asserted, they

must respond by snooping any addresses broadcast. Normally, GBL reflects the M bit value specified for

the memory reference in the corresponding translation descriptor. Care must be taken to minimize the

number of pages marked as global, because the retry protocol discussed in the previous section used to

enforce coherency can require significant bus bandwidth.

CLKOUT

ADDR + ATTR

AACK

DBG

Data

TEA

For Single

For Burst

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