MPC8280 datasheet(325/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-17

When the CONFIG_ADDRESS register gets written with a value such that the bus number matches the

bridge’s bus, the device number is all ones, the function number is all ones and the register number is zero,

the next time the CONFIG_DATA register is accessed the PCI bridge does either a special cycle or an

interrupt acknowledge command. When the CONFIG_DATA register is written, the PCI bridge generates

a special cycle encoding on the command/byte enable lines during the address phase, and drives the data

from the CONFIG_DATA register onto the address/data lines during the first data phase.

If the bus number field of the CONFIG_ADDRESS does not match one of the PCI bridge’s bus numbers,

the PCI bridge passes the write to CONFIG_DATA on through to the PCI bus as a type 1 configuration

cycle like any other time the bus number field does not match.

9.9.1.4.7

Interrupt Acknowledge

When the CONFIG_ADDRESS register gets written with a value such that the bus number is 0x00, the

device number is all ones, the function number is all ones and the register number is zero, the next time

the CONFIG_DATA register is accessed the PCI bridge does either a special cycle command or an

interrupt acknowledge command. When the CONFIG_DATA register is read, the PCI bridge generates an

interrupt acknowledge command encoding on the command/byte enable lines during the address phase.

During the address phase, AD[31-0] do not contain a valid address but are driven with stable data and valid

parity (PAR). During the data phase, the byte enable signals determine which bytes are involved in the

transaction. The interrupt vector must be returned when TRDY is asserted.

An interrupt acknowledge transaction can also be issued on the PCI bus by reading from the

PCI_INT_ACK register.

9.9.1.5

Error Functions

This section discusses PCI bus errors.

9.9.1.5.1

Parity

During valid 32-bit address and data transfers, parity covers all 32 address/data lines and the 4

command/byte enable lines regardless of whether or not all lines carry meaningful information. Byte lanes

not actually transferring data are driven with stable (albeit meaningless) data and are included in the parity

calculation. During configuration, special cycle or interrupt acknowledge commands, some address lines

are not defined but are still driven to stable values and included in the parity calculation.

Even parity is calculated for all PCI operations: the value of PAR is generated such that the number of ones

on AD[31-0], PCI_C/BE[3-0] and PAR equals an even number. PAR is driven when the address/data lines

are driven and follow the corresponding address or data by one clock.

The PCI bridge checks the parity after all valid address phases (the assertion of FRAME) and for valid data

transfers (IRDY and TRDY asserted) involving the PCI bridge. When an address or data parity error is

detected, the detected-parity-error bit in the configuration space status register is set (see Section 9.11.2.4,

“PCI Bus Status Register”).

MPC8280 Datasheet(PDF) 325 Page - Freescale Semiconductor, Inc

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