MPC8280 datasheet(321/1386 Pages) FREESCALE

321 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-13

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AD[1-0] is 0bx1 (a reserved burst ordering encoding) during the address phase and one data phase

has completed.

•

The PCI command is a configuration command and one data phase has completed when a

streaming transaction crosses a 4K page boundary.

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A streaming transaction runs out of I/O sequencer buffer entries.

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A cache line wrap transaction has completed a cache line transfer.

Another target-initiated termination is the retry termination. Retry refers to termination requested because

the target is currently in a state where it is unable to process the transaction. This can occur because no

buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without

transfer of the first data. The target latency timer of the PCI bridge can be optionally disabled see

Section 9.11.2.22, “PCI Bus Function Register.”

When the PCI bridge is in host mode it does not respond to any PCI configuration transactions. When the

PCI bridge is in agent mode and AGENT_CFG_LOCK is set (refer to Section 9.11.2.22, “PCI Bus

Function Register”) the PCI bridge will retry all configuration transactions. Note that all retried accesses

need to be completed. An example of a retry is shown in Figure 9-7.

Note that because a target can determine whether or not data is transferred (when both IRDY and TRDY

are asserted), if it wants to do only one more data transfer and then stop, it may assert TRDY and STOP at

the same time.

Target-abort refers to the abnormal termination that is used when a fatal error has occurred, or when a

target will never be able to respond. Target-abort is indicated by the fact that STOP is asserted and

DEVSEL is negated. This indicates that the target requires the transaction to be terminated and does not

want the transaction tried again. Note that any transferred data may have been corrupted.

The PCI bridge terminates a transaction with target-abort in the case in which it is the intended target of a

read transaction from system memory and the data from memory is corrupt. If the PCI bridge is the

intended target of a transaction and an address parity error occurs, or a data parity error occurs on a write

transaction to system memory, it continues the transaction on the PCI bus but aborts internally. The PCI

bridge does not target-abort in this case.

If the PCI bridge is mastering a transaction and the transaction terminates with a target-abort, undefined

data will be returned on a read and write data will be lost. An example of a target-abort is shown in

Figure 9-7.

An initiator may retry any target disconnect accesses, except target-abort, at a later time starting with the

address of the next non-transferred data. Retry is actually a special case of disconnect where no data

transfer occurs at all and the initiator must start the entire transaction over again.

9.9.1.4

Other Bus Operations

The following sections provide information on additional PCI bus operations.

9.9.1.4.1

Device Selection

As a target, the PCI bridge drives DEVSEL one clock following the address phase as indicated in the

configuration space status register; see Section 9.11.2.4, “PCI Bus Status Register.” The PCI bridge as a

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