MPC8280 datasheet(389/1386 Pages) FREESCALE

389 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-81

9.12.3.4.4

Outbound Message Interrupt Mask Register (OMIMR)

OMIMR contains the interrupt mask of the I2O, door bell, and message register events generated by the

local processor. OMIMR should be accessed only from the PCI bus.

Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR)

Table 9-61 describes OMIMR fields.

OM1I

Read/

Write 1

to clear

Outbound message 1 interrupt. When set indicates that there is an Outbound

message 1 interrupt.

OM0I

Read/

Write 1

to clear

Outbound message 0 interrupt. When set indicates that there is an Outbound

message 0 interrupt

1 Note that when conditions for the Outbound Post Queue Interrupt assertion are valid, and OMIMR[OPQIM] is set,

OMISR[OPQI] is cleared. The application should always clear OMIMR[OPQIM] before referring to the content of

OMISR[OPQI].

Field

—

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-61.

Addr

0x10436

654

Field

—

OPQIM

—ODIM

—

OM1IM OM0IM

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-61.

Addr

0x10434

Table 9-61. OMIMR Field Descriptions

Bits

Name

R/W

Description

31–6

—

Reserved, should be cleared.

OPQIM

Outbound post queue interrupt mask

0 Outbound post queue interrupt is allowed.

1 Outbound post queue interrupt is masked.

—

Reserved, should be cleared.

ODIM

Outbound doorbell interrupt mask

0 Outbound doorbell interrupt is allowed.

1 Outbound doorbell interrupt is masked.

—

Reserved, should be cleared.

Table 9-60. OMISR Field Descriptions (continued)

Bits

Name

R/W

Description

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