MPC8280 datasheet(551/1386 Pages) FREESCALE

551 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

14-1

Chapter 14

Communications Processor Module Overview

The MPC8280’s communications processor module (CPM) is a superset of the MPC860 PowerQUICC

CPM, with enhancements in performance. The support for multiple HDLC channels is enhanced to support

up to 256 HDLC channels.

14.1

Features

The CPM includes various blocks to provide the system with an efficient way to handle data

communication tasks. The following is a list of the CPM’s important features.

•

Communications processor (CP)

— One instruction per clock

— Executes code from internal ROM or dual-port RAM

— 32-bit RISC architecture

— Tuned for communication environments: instruction set supports CRC computation and bit

manipulation.

— Internal timer

— Interfaces with the embedded G2_LE core processor through a dual-port RAM and virtual

DMA channels for each peripheral controller.

— Handles serial protocols and virtual DMA.

•

Three full-duplex fast serial communications controllers (FCCs) support the following protocols:

— ATM protocol through UTOPIA interface (FCC1 and FCC2 only) (Not on MPC8270)

— IEEE802.3/Fast Ethernet

— HDLC

— Totally transparent operation

•

Two multi-channel controllers (MCCs) (only MCC2 on the MPC8270 and the MPC8275) that

together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to

eight TDM interfaces

•

Four full-duplex serial communications controllers (SCCs) support the following protocols:

— IEEE 802.3/Ethernet

— High level/synchronous data link control (HDLC/SDLC)

— LocalTalk (HDLC-based local area network protocol)

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART (1x clock mode)

MPC8280 Datasheet(PDF) 551 Page - Freescale Semiconductor, Inc