MPC8280 datasheet(554/1386 Pages) FREESCALE

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Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

14-4

Freescale Semiconductor

14.3

Communications Processor (CP)

The communications processor (CP), also called the RISC microcontroller, is a 32-bit controller for the

CPM that resides on a separate bus from the core and, therefore, can perform tasks independent of the

G2_LE core. The CP handles lower-layer communications tasks and DMA control, freeing the core to

handle higher-layer activities. The CP works with the peripheral controllers and parallel port to implement

user-programmable protocols and manage the serial DMA (SDMA) channels that transfer data between

the I/O channels and memory. It also manages the IDMA (independent DMA) channels and contains an

internal timer used to implement up to 16 additional software timers.

The CP’s architecture and instruction set are optimized for data communications and data processing

required by many wire-line and wireless communications standards.

14.3.1

CPM Performance Evaluation

Because the CP is a single shared resource used by all of the CPM’s communications peripherals, the

combined service requests from all of the communications peripherals must not exceed the CP’s capacity.

The amount of processing required by a particular communications peripheral depends on the mode in

which the peripheral is configured and the maximum rate at which the channel requests service. To

determine if CPM performance and bus bandwidth consumption of a given configuration is valid, users

should consult the “MPC8280 CPM Performance Evaluator,” which is located under “Application

Software” on a device’s product page at www.freescale.com.

14.3.2

Features

The following is a list of the CP’s important features.

•

One system clock cycle per instruction

•

32-bit instruction object code

•

Executes code from internal ROM or RAM

•

32-bit ALU data path

•

64-bit dual-port RAM access

•

Optimized for communications processing

•

Performs DMA bursting of serial data from/to dual-port RAM to/from external memory. Note that

IDMA cannot burst to dual-port RAM.

ATM access

ATM

FEnet

E3 or E1’s E3 or E1’s ATM

UART

GSM mobile

switching center

E1’s

FEnet or

ATM

Backbone

10 M

HDLC

10 M

HDLC

1 Not on the MPC8270 and the MPC8275.

Table 14-1. Possible MPC8280 Applications (continued)

Application

MCC11

MCC2

FCC1

FCC2

FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2

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