MPC8280 datasheet(557/1386 Pages) FREESCALE

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Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

14-7

14.3.4

G2_LE Core Interface

The CP communicates with the G2_LE core in several ways:

•

Many parameters are exchanged through the dual-port RAM.

•

The CP can execute special commands issued by the core. These commands should only be issued

in special situations like exceptions or error recovery.

•

The CP generates interrupts through the SIU interrupt controller.

•

The G2_LE core can read the CPM status/event registers at any time.

14.3.5

Peripheral Interface

The CP uses the peripheral bus to communicate with all of its peripherals. Each FCC and each SCC has a

separate receive and transmit FIFOs. The FCC FIFOs are 192 bytes. The SCC FIFOs are 32 bytes. The

SMCs, SPI, and I2C are all double-buffered, creating effective FIFO sizes of two characters.

Table 14-2 shows the order in which the CP handles requests from peripherals from highest to lowest

priority.

NOTE: Emergency Prioritization

Elevation to emergency status (priority 4) is determined on per peripheral

basis and may depend on a peripheral’s mode of operation. Emergency

prioritization among peripherals maintains relative normal prioritization.

For example, simultaneous emergency requests from FCC1 transmit and

MCC2 transmit would be handled in the same order as normal requests

(FCC1 transmit).

Table 14-2. Peripheral Prioritization

Priority

Request

Reset in the CPCR or SRESET

2SDMA bus error

Commands issued to the CPCR

Emergency (from FCCs, MCCs, and SCCs)

IDMA[1–4] emulation (default—option 1)1

USB receive

USB transmit

FCC1 receive

FCC1 transmit

MCC1 receive2

MCC2 receive

MCC1 transmit2

MCC2 transmit

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