MPC8280 datasheet(559/1386 Pages) FREESCALE

559 / 1386 page

Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

14-9

14.3.7

RISC Controller Configuration Register (RCCR)

The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures the CP to run

microcode from ROM or RAM and controls the CP’s internal timer.

RCCR bit fields are described in Table 14-3.

Field TIME

MCCPR

TIMEP

DR1M DR2M DR1QP

EIE

SCD

DR2QP

Reset

0000_0000_0000_0000

R/W

Addr

0x119C4

Field

ERAM

EDM1 EDM2 EDM3

EDM4 DR3M DR4M DR3QP DEM12 DEM34 DR4QP

Reset

0000_0000_0000_0000

R/W

Addr

0X119C6

Figure 14-3. RISC Controller Configuration Register (RCCR

Table 14-3. RISC Controller Configuration Register Field Descriptions

Bits

Name

Description

TIME

Timer enable. Enables the CP internal timer that generates a tick to the CP based on the value

programmed into the TIMEP field. TIME can be modified at any time to start or stop the scanning

of the RISC timer tables.

MCCPR

MCC request priority. Controls the priority of the MCCs in relation to the other communication

peripherals. See Table13-2. “Peripheral Prioritization,” for more information.

0 Original CPM priority scheme. MCCx priority behaves according to Table 13-2.

1 MCC priority remains at emergency level, priority level 4.

2–7

TIMEP

Timer period controls the CP timer tick. The RISC timer tables are scanned on each timer tick and

the input to the timer tick generator is the general system clock (133/166MHZ) divided by 1,024.

The formula is (TIMEP + 1)

× 1,024 = (general system clock period). Thus, a value of 0 stored in

these bits gives a timer tick of 1

× (1,024) = 1,024 general system clocks and a value of 63

(decimal) gives a timer tick of 64

× (1,024) = 65,536 general system clocks.

8, 9,

24, 25

xMIDMAx request mode. Controls the IDMA request x (DREQx) sensitivity mode. DREQx is used to

activate IDMA channel

x. See Section 19.7, “IDMA Interface Signals.”

0 DREQ

x is edge sensitive (according to EDMx).

1 DREQ

x is level sensitive.

Note: When DRxM is set to level mode, EDMx determines if IDMA request is active high or active

low. Refer to description of RCCR[20–24].

Note: If RCCR[EIE] = 1, RCCR[DR1M] must be reset. No external interrupt occurs otherwise.

10–11,

14–15,

26–27,

30–31

xQP

IDMA

x request priority. Controls the priority of DREQx relative to the communications controllers.

See Section 19.7, “IDMA Interface Signals.”

00 DREQ

x has more priority than the communications controllers (default).

01 DREQ

x has less priority than the communications controllers (option 2).

10 DREQ

x has the lowest priority (option 3).

11 Reserved

MPC8280 Datasheet(PDF) 559 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 559 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL