MPC8280 datasheet(563/1386 Pages) FREESCALE

563 / 1386 page

Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

14-13

Table 14-6 describes CPCR fields.

Table 14-6. CP Command Register Field Descriptions

Bit

Name

Description

RST

Software reset command. Set by the core and cleared by the CP. When this command is executed,

RST and FLG bit are cleared within two general system clocks. The CPM reset routine is

approximately 60 clocks long, but the user can begin initialization of the CPM immediately after

this command is issued.

RST is useful when the core wants to reset the registers and parameters for all the channels

(FCCs, SCCs, SMCs, SPI, I

2C, MCC) as well as the CP and RISC timer tables. However, this

command does not affect the serial interface (SI

x) or parallel I/O registers.

1–5

PAGE

Indicates the parameter RAM page number associated with the sub-block being served. See the

SBC description for page numbers.

6–10

SBC

Sub-block code. Set by the core to specify the sub-block on which the command is to operate. Set

according to OPCODE[28-31]. Refer to Table 13-7.

Sub-block

Code

Page

Sub-block

Code

Page

FCC11

01110: ATM transmit

(OPCODE = 1010)

10000: all other commands

00100

SPI

01010

01001

FCC21

01110: ATM transmit

(OPCODE = 1010)

10001: all other commands

00101

I2C

01011

01010

FCC3

10010

00110

Timer

01111

01010

SCC1

00100

00000

MCC12

11100

00111

SCC2

00101

00001

MCC2

11101

01000

SCC3

00110

00010

IDMA1

10100

00111

SCC4

00111

00011

IDMA2

10101

01000

SMC1

01000

00111

IDMA3

10110

01001

SMC2

01001

01000

IDMA4

10111

01010

RAND

01110

01010

USB

10011

01011

11–14

—

Reserved

FLG

Command semaphore flag. Set by the core and cleared by the CP.

0 The CP is ready to receive a new command.

1 The CPCR contains a command that the CP is currently processing. The CP clears this bit at

the end of command execution or after reset.

16–17

—

Reserved

18–25

MCN

MCC channel number. Specifies the channel number in the case of an MCC command.

In FCC protocols, this field contains the protocol code as follows:

0x00 HDLC, Transparent

0x0A ATM3

0x0C Ethernet

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