MPC8280 datasheet(560/1386 Pages) FREESCALE

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Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

14-10

Freescale Semiconductor

14.3.8

RISC Time-Stamp Control Register (RTSCR)

The RISC time-stamp control register (RTSCR), shown in Figure 14-4, configures the RISC time-stamp

timer (RTSR). The time-stamp timer is used by the ATM and the HDLC controllers. For application

examples, see Section 31.5.3, “ABR Flow Control Setup,” and Section 37.6, “HDLC Mode Register

(FPSMR).”

EIE

External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP.

Configure as instructed in the download process of a Freescale-supplied RAM microcode

package.

0 DREQ1 cannot interrupt the CP.

1 DREQ1 will interrupt the CP.

Note: If EIE = 1, DR1M must be reset. No external interrupt occurs otherwise.

Note: External CPM RISC interrupt must be connected to DREQ1 and DREQ4.

SCD

Scheduler configuration. Configure as instructed in the download process of a Freescale-supplied

RAM microcode package.

0 Normal operation

1 Alternate configuration of the scheduler, according to bit 19 (in the ERAM field):

If RCCR[19] = 0, the jump table starts at dual-port RAM address 0x0000.

If RCCR[19] = 1, the jump table starts at dual-port RAM address 0x4000.

16–19

ERAM

Enable RAM microcode. Configure this field as instructed during the downloading process of a

Freescale-supplied RAM microcode package. Otherwise, it should not be used.

0000 Disable microcode program execution from the internal RAM.

0100 Microcode is executed from the Instruction RAM.

Other combinations of these bits are not valid and must not be used.

20, 21,

22, 23

EDM

Edge detect mode. DREQ

x asserts as follows:

0 Low-to-high change

1 High-to-low change

Note: When DRxM is set to level mode:

0 DRxM is active high

1 DRxM is active low.

DEM12

Edge detect mode for DONE[1, 2] for IDMA[1, 2]. See Section 19.7.2, “DONEx.” DONE[1, 2]

asserts as follows:

0 High-to-low change

1 Low-to-high change

DEM34

Edge detect mode for DONE[3, 4] for IDMA[3, 4]. See Section 19.7.2, “DONEx.” DONE[3, 4]

asserts as follows:

0 High-to-low change

1 Low-to-high change

Table 14-3. RISC Controller Configuration Register Field Descriptions (continued)

Bits

Name

Description

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