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MPC8280 Datasheet(PDF) 619 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 619 Page - Freescale Semiconductor, Inc

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CPM Multiplexing
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
16-7
NOTE
After a clock source is selected, the clock is given an internal name. For the
FCCs and SCCs, the names are RCLKx and TCLKx; for SMCs, the name is
simply SMCLKx. These internal names are used only in NMSI mode to
specify the clocks sent to the FCCs, SCCs or SMCs. These names do not
correspond to any MPC8280 pins.
16.4
CMX Registers
The following sections describe the CMX registers.
16.4.1
CMX UTOPIA Address Register (CMXUAR)
NOTE
This section does not apply to the MPC8270.
The CMX UTOPIA address register (CMXUAR), shown in Figure 16-4, defines the connection of FCC1
and FCC2 UTOPIA multiple-PHY addresses to the twenty UTOPIA address pins of the MPC8280; it also
defines the connection of a BRG to the FCCs when an internal rate feature is used. This enables the user
to implement a multiple-PHY UTOPIA master or slave on both FCC1 and FCC2 using only twenty pins.
The user chooses how many PHYs to use with each interface and how many address lines are needed for
each FCC.
Table 16-2 describes CMXUAR fields.
01234
5
6
7
8
9
10
11
12
15
Field SAD0 SAD1 SAD2 SAD3 SAD4
—
MAD4 MAD3
F1IRB
F2IRB
—
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x11B0E
Figure 16-4. CMX UTOPIA Address Register (CMXUAR)
Table 16-2. CMXUAR Field Descriptions
Bits
Name
Description
0–4
SAD
x
Slave address input pin
x connection. Note that the address indexes are relative to FCC1; see
Figure 16-7.
0 This address input pin is used by FCC2 in slave mode.
1 This address input pin is used by FCC1 in slave mode.
5
—
Reserved, should be cleared.
6–7
MAD
x
Master address output pin
x connection. Note that the address indexes are relative to FCC1; see
Figure 16-7.
0 This address output pin is used by FCC2 in master mode.
1 This address output pin is used by FCC1 in master mode.
Note: Setting both MAD3 and MAD4 to 1 enables a special extended PHY mode (see Section
31.12.3, “Extended Number of PHYs”).



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