MPC8280 datasheet(1065/1386 Pages) FREESCALE

1065 / 1386 page

ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

32-5

received octet becomes the first byte of the new BD (new super frame). (See Section 32.5, “ATM-to-TDM

Adaptive Slip Control” and Section 32.4, “Interworking Functions.”)

Note that when the ATM channel is not in CES mode, no restart sequence is performed; the ATM receiver

immediately starts hunting for the first valid cell. The first received octet becomes the first byte of the next

BD.

During reassembly, the ATM receiver channel’s 3-step-SN algorithm status is delivered to the pointer

verification mechanism. (See Section 32.7, “Pointer Verification Mechanism.”) If the receiver operates in

unstructured data format, the 3-step-SN algorithm status is delivered directly to the bit count integrity

module. When partially filled cells arrive, the bit count integrity module copies only the valid octets from

the received cell (or from the dummy cell if that cell is lost) to the current receive buffer.

In unstructured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a

valid sequence number (SN field). When one arrives, the receiver leaves the hunt state and begins

receiving incoming cells.

In structured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a

valid structured pointer (not a dummy pointer), that points to the start of a new structure. When one arrives,

the receiver leaves the hunt state, opens a new buffer and begins receiving. The structured pointer points

to the first octet of the structured block, which then becomes the first byte of the new buffer.

During the reassembly process, if the receiver switches to hunt mode (due to the 3-step-SN algorithm or

due to receiving two successive mismatched pointers), the ATM receiver closes the current RxBD,

discards incoming cells, modifies the receive statistics accordingly and initiates a restart sequence. The

receiver then waits for a cell with a valid structured pointer to regain synchronization and start receiving

incoming cells again.

The MPC8280 supports SRTS clock recovery using an external PLL. The MPC8280 tracks the SRTS from

the four incoming cells and writes the SRTS code to external logic. See Section 31.16, “SRTS Generation

and Clock Recovery Using External Logic.” The data flow for an AAL1 CES receiver is summarized in

Figure 32-4.

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