MPC8280 datasheet(1087/1386 Pages) FREESCALE

1087 / 1386 page

ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

32-27

Table 32-5 describes RCT fields.

Table 32-5. RCT Field Descriptions

Offset

Bits

Name

Description

0x00

0–1

—

Reserved, should be cleared during initialization.

GBL

Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free

buffer pool.

3–4

Byte ordering—used for data buffers.

00 Reserved

01munged little endian

1x Big endian

—

Reserved, should be cleared during initialization.

DTB

Data buffers bus

0 Data buffers reside on the 60x bus.

1 Data buffers reside on the local bus.

BIB

BD interrupt queues, free buffer pool, and CES external statistics tables bus placement

0 Reside on the 60x bus.

1 Reside on the local bus.

Notes:

1. When in UDC mode (AAL5 or AAL1 or AAL1 CES), BDs and data should be placed

on the same bus (RCT[DTB]=RCT[BIB]).

2. RCT[BIB] programming must be consistent across all CES receive channels

because they share the same AAL1_Ext_STATT_BASE parameter.

8–9

—

Reserved, should be cleared during initialization.

SEGF

OAM F5 segment filtering

0 Do not send cells with PTI=100 to the raw cell queue.

1 Send cells with PTI=100 to the raw cell queue.

ENDF

OAM F5 end-to-end filtering

0 Do not send cells with PTI=101 to the raw cell queue.

1 Send cells with PTI=101 to the raw cell queue.

—

Reserved, should be cleared during initialization.

SYNC

AAL1 SYNC. The user should set this bit for first AAL1 synchronization. Used internally

by the CP.

14–15

INTQ

Points to one of four interrupt queues available.

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