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MPC8280 Datasheet(PDF) 1127 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1127 Page - Freescale Semiconductor, Inc |
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1127 / 1386 page ![]() ATM AAL2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-21 • RxQD offsets from 8 through 511 point into the internal RxQD table located in dual-port RAM at RxQD_Base_Int. Note that the first 32 bytes of the internal RxQD table are reserved (so offsets 0–7 are reserved). • RxQD offsets greater than 511 point into the external RxQD table located at RxQD_Base_Ext + (512*4). • Because the three types of RxQDs are different sizes, some offset numbers may not be used. Figure 33-13. CID Mapping Process 33.4.3 AAL2 Switching Switching is performed by pointing an RX CID at a switch RxQD (see Figure 33-14). The switch RxQD is unique for each Rx CID. The descriptor holds a translation CID number and a pointer to a CPS TxQD into which this packet is saved and later sent by the transmitter. (The TxQD pointer is responsible for the actual PHY | VP | VC switching.) The TxQD pointed to by the switch RxQD(s) should have TxQD[SW] set and should not be modified by the host when the channel is active. The transmit scheduling of the packet is done by the APC according to the programmed bit rate of the ATM channel that holds the switched queue. RxQD table (internal) 0 32 64 72 2044 Reserved SSSAR RxQD CPS RxQD Switch RxQD RxQD table (external) 2048 CPS RxQD Switch RxQD RxBD table RxBD table Tx queue descriptor TxBD table Rx buffers Rx buffers Tx buffers RxQD_Base_Int + RxQD_Offset*4 CID mapping table RxQD offset RxQD offset CID0 CID1 CID255 RxQD_Base_Ext + 512*4 (in FCC parameter RAM) RxQD offset RxQD offset • • • Half-word CID mapping table base RxQD_Base_Int (in FCC parameter RAM) AAL2 RCT ATM cell Header STF CID-PH CPS packet payload CID-PH CPS packet payload |
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