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MPC8280 Datasheet(PDF) 1169 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1169 Page - Freescale Semiconductor, Inc

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Inverse Multiplexing for ATM (IMA)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
34-23
NOTE
IMAROOT must be programmed to a 128-byte aligned address terminating
with 0x80 (i.e. 0xnn80).
34.4.3
IMA Root Table
Table 34-3. IMA Root Table1
Offset
Name
Width
Description
0x04
IMAFILLERHD2
4 Bytes
Filler cell template. Used by microcode in transmission of filler cells. The
cell is formatted as byte-swapped, and additionally the header is
bitswapped. [This is due to hardware implementation, and does not imply
the order of the transmission of the cell. The transmission of the cell is per
the ATM standard.]
Content should be:
0xD0000000 (header)
0x6A6A0001 or 0x6A6A0003 (for IMA Version 1.0 or 1.1)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0xC6026A6A or 0xD9026A6A (for IMA Version 1.0 or 1.1)
0x00–
0x2F
IMAFILLERPLD
48 Bytes
0x30
FILLTAG
Byte
Tag indicating that the filler template is a filler cell. Program to zero.
0x31
TQ_SIZE
Byte
Transmit queue size. Recommended value is 0x18. Must be a multiple of 4.
Refer to Section 34.4.6.1, “Transmit Queues for more details
0x32
TQ_TARGET
Byte
Transmit queue target level. Recommended value is 0x0C. Must be a
multiple of 4.
0x33
TQ_THRESHOLD Byte
Transmit queue stuff threshold. Recommended value is 0x0C. Must be a
multiple of 4.
0x34
RESERVED
Hword
Reserved.
0x36
IMACNTL
Byte
IMA control parameter. Controls functions shared by all IMA groups for this
FCC.
0x37
TMP_PCNT
Byte
Microcode managed parameter (pass count).
0x38
RXPHYEN
Word
Receive PHY enable. Bit array addressed by PHY address (e.g. bit 0
corresponds to PHY 0). Setting a bit enables reception for the
corresponding PHY. Must be used to enable/disable the corresponding
PHY regardless of whether or not the PHY is defined as IMA in IMAPHY.
All cells received by disabled PHYs are discarded. Note that the FCC must
also be enabled in GFMR[ENR] for reception to occur.
Bit 31 is reserved, and must be programmed to zero.



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