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MPC8280 Datasheet(PDF) 1178 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1178 Page - Freescale Semiconductor, Inc |
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1178 / 1386 page  Inverse Multiplexing for ATM (IMA) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-32 Freescale Semiconductor 0x07 RSCCI Byte Receive IMA SCCI field. Microcode-managed parameter. Holds the SCCI value of the last ICP cell received by this group. 0x08 DCBLNK Hword Pointer to link entry in group order table currently in use. Microcode-managed parameter. Initialize to value of RGRPORDER0 at group startup. 0x0A DCBX Hword Delay-compensation buffer extraction pointer. Microcode-managed parameter. Initialize to zero at group startup. 0x0C STALL_COUNT Byte Number of IDCR or On-demand requests made for which there were no cells available in a link’s DCB. Microcode managed parameter. Initialize to zero at group startup. 0x0D REF_IFSN Byte Identifies the IFSN of the frame being processed by the “reconstruction” routine. Microcode managed parameter. 0x0E GFP Hword Pointer to the start of the current frame being processed by the “reconstruction” routine. Microcode managed parameter. Initialize to zero at group startup. 0x10 RGRPORDER0 Hword Offset of receive group order table 0 in DPRAM. 0x12 RGRPORDER1 Hword Offset of receive group order table 1 in DPRAM. 0x14 ALPHABETA Byte Alpha and beta parameters for IMA frame synchronization mechanism (IFSM). Bits 0-3: Alpha. Allowable range is 1-2; typical value is 2. Bits 4-7: Beta. Allowable range is 1-5; typical value is 2. 0x15 GAMMA Byte Gamma parameter for IMA frame synchronization mechanism (IFSM). Allowable range is 1-5; typical value is 1. 0x16 TRLR Hword TRL rate. Used only when IDCR-regulated cell processing is used (i.e. IGRCTNL[IDCR]=1). Calculated by microcode during group startup, prior to group activation. Referenced by software in order to program the IDCRREQ and IDCRREQF of the group’s IDCR table entry. Value is valid after IGRSTATE[IDCR_DN] is set by the microcode. 0x18 REF_LINK Word Bit array identifying which of the links (i.e., PHY) in this group are enabled. Bit 0 corresponds to PHY 0, bit 30 corresponds to PHY 30. Software must set the corresponding bits to 1 so that the delay compensation process for the link(s) is started. 0x1C LINK_ICP Word Bit array identifying which of the links in this group has received an ICP cell. A “1” in the corresponding link’s bit position indicates that an ICP cell has been received. Microcode-managed parameter. Initialize to zero at group startup. 0x20 LINK_DCB Word Bit array identifying which of the links in this group has started storing cells to its corresponding DCB. A “1” in the corresponding link’s bit position indicates that cells have been stored in the DCB. Microcode-managed parameter. Initialize to zero at group startup. Table 34-10. IMA Group Receive Table Entry (continued)1 Offset Name Width Description |
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