MPC8280 datasheet(1181/1386 Pages) FREESCALE

1181 / 1386 page

Inverse Multiplexing for ATM (IMA)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

34-35

Table 34-12 describes the IGRSTATE bit fields.

34.4.4.2.3

IMA Receive Group Frame Size

The fields of the IRGFS register are shown in Figure 34-19.

Table 34-13 describes the IRGFS bit fields.

34.4.4.2.4

Receive Group Order Tables

The receive group order tables define the order of the links in the round-robin extraction of cells to the

links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each

byte providing the PHY address of its associated link. The end of the table is indicated by an entry

programmed to 0x1F.

Two group order tables are used in order to allow for on-the-fly changes (i.e. to add or remove links), while

making certain that the changes only occur at the end of a round-robin cycle. IGRCNTL[GOTP] indicates

which group order table pointer (and therefore, group table) is currently in use. Changes should be made

Table 34-12. IGRSTATE Field Descriptions

Bits

Name

Description

IDCR_DN

IDCR Done. Microcode-managed parameter. When this bit is set by the microcode, the TRLR

value is valid and can be used to program the IDCR timer entry values for this group. Initialize

to zero at group startup.

1–2

GDSS

Group delay synchronization state. Initialize to zero at group startup. Must be changed by

software to 01 after sufficient links have achieved frame synchronization. Subsequently

managed by microcode.

00 Group delay synchronization process inhibited.

01 Group delay synchronization process enabled.

10 Group delay synchronization process in progress.

11 Group delay synchronized.

Refer to Section 34.5.4.10, “Receive Event Response Procedures".

3–7

—

Reserved, initialize to zero.

Field

—

GSC-M

Figure 34-19. IMA Receive Group Frame Size (IGRSTATE)

Table 34-13. IRGFS Field Descriptions

Bits

Name

Description

Reserved, initialize to zero.

1–5

—

Reserved, initialize to zero.

6–7

GSC-M

IMA Receive Group Frame Size

Bits 0-5: Reserved

Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field

(Bits 1:0) which determine the IMA frame size. This field must be

programmed before links in the group are assigned

MPC8280 Datasheet(PDF) 1181 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1181 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL