MPC8280 datasheet(1183/1386 Pages) FREESCALE

1183 / 1386 page

Inverse Multiplexing for ATM (IMA)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

34-37

34.4.5.1.1

IMA Link Transmit Control (ILTCNTL)

The fields of the ILTCNTL register are shown in Figure 34-21.

0x03

ILID

Byte

IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell.

Bit 0: 1 (indicating ICP cell)

Bits 1-2: Not Used, set to zero

Bits 3-7: Program to software-assigned LID.

[Note: This value is only used by microcode to format ICP cells for this

link, it is not used to determine round-robin transmission order. That

function is performed by the group order table.]

0x04

ITSEC

Word

IMA transmit stuff event counter. While ILTCNTL[SES]=0, increments

each time a stuff event is performed on this link. Initialize to zero at link

startup.

0x08

ITQSP

Hword

IMA link transmit queue start pointer. This parameter forms bits 12-27

of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are

zero. Refer to Section 34.4.6.1, “Transmit Queues".

0x0A

ITQEP

Hword

IMA link transmit queue end pointer. This parameter forms bits 12-27

of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are

zero. Points to the last cell in the transmit queue. Program this

parameter to ITQSP+TQ_SIZE-4. Refer to Section 34.4.6.1, “Transmit

Queues".

0x0C

ITQFP

Hword

IMA link transmit queue fill pointer. This parameter forms bits 12-27 of

the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero.

Initialize this to the value of ITQSP. Refer to Section 34.4.6.1, “Transmit

Queues".

0x0E

ITQXP

Hword

IMA link transmit queue extract pointer. This parameter forms bits

12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31

are zero. Initialize this to the value of ITQSP. Refer to Section 34.4.6.1,

“Transmit Queues“.

0x10

ITINTMSK

Byte

IMA transmit interrupt mask. Has the same format as the upper byte of

the IMA interrupt queue entry. Setting a bit enables the associated

interrupt; clearing a bit masks it.

For group-related events, only the mask register for the TRL is

referenced.

0x11

ITINTSTAT

Byte

IMA transmit interrupt status. Indicates the status of transmit interrupt

events.

0x12

LSHC

Byte

Stuff holdoff counter. Maintains the minimum five-frame spacing

between stuff events for non-TRL links. Must be initialized to zero. Set

to 4 by the microcode after a stuff event, and decrements after each

ICP cell is sent (saturating at zero). Signalling of ‘imminent stuff’ (and

subsequent stuff events) will not occur while this counter is non-zero.

1 Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are

managed by the microcode and should be initialized to zero unless otherwise stated.

Table 34-15. IMA Link Transmit Table Entry (continued)1

Offset

Name

Width

Description

MPC8280 Datasheet(PDF) 1183 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1183 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL