MPC8280 datasheet(1240/1386 Pages) FREESCALE

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Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-6

Freescale Semiconductor

There is one internal buffer for out-of-sequence flow control frames (in full-duplex Fast Ethernet). When

the Fast Ethernet controller is between frames, this buffer is polled if flow control is enabled. This buffer

must contain the whole frame.

However, in half-duplex mode, the controller defers transmission if the line is busy (CRS asserted). Before

transmitting, the controller waits for carrier sense to become inactive, at which point the controller

determines if CRS remains negated for 16 serial clocks. If so, the transmission begins after an additional

8 serial clocks (96 bit-times after CRS originally became negated). In the fast ethernet transmitter, if CRS

is asserted and then negated within 10 clocks after TXEN is negated, the next frame is not deferred and a

defer indication is asserted.

If a collision occurs during the transmit frame, the Ethernet controller follows a specified backoff

procedure and tries to retransmit the frame until the retry limit is reached. The Ethernet controller stores

at least the first 64 bytes of data of the transmit frame in the FCC FIFO, so that the data does not have to

be retrieved from system memory in case of a collision. This improves bus usage and latency if the backoff

timer output requires an immediate retransmission.

When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes are appended

(if TxBD[TC] = 1), and TX_EN is negated. This notifies the PHY of the need to generate the illegal

Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS,

the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. When the end of the

current buffer is reached and TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is

cleared.

For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet

controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each

frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD] = 1, the Ethernet controller pads

short frames to the value of the minimum frame length register (MINFLR), described in Table 36-2.

To rearrange the transmit queue before the CP finishes sending all frames, issue a GRACEFUL STOP

TRANSMIT

command. This can be useful for transmitting expedited data ahead of previously linked buffers

or for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller

stops immediately if no transmission is in progress or continues transmission until the current frame either

finishes or terminates with a collision. When the Ethernet controller is given the RESTART TRANSMIT

command, it resumes transmission. The Ethernet controller sends bytes least-significant nibble first.

36.5

Ethernet Channel Frame Reception

The Ethernet receiver is designed to work with almost no core intervention and can perform address

recognition, CRC checking, short frame checking, maximum DMA transfer checking, and maximum

frame-length checking.

When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted as long as COL

remains negated (full-duplex mode ignores COL). In hunt mode, as data is shifted into the receive shift

the FCC’s data synchronization register (FDSR). When the registers match, the hunt mode is terminated

and character assembly begins.

MPC8280 Datasheet(PDF) 1240 Page - Freescale Semiconductor, Inc

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