MPC8280 datasheet(1253/1386 Pages) FREESCALE

1253 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

36-19

Reception errors are described in Table 36-7.

36.18 Fast Ethernet Registers

The following sections describe registers used for configuring and operating the Fast Ethernet controller.

36.18.1 FCC Ethernet Mode Registers (FPSMR

The MPC2880 supports 10/100 Mbps Ethernet through a RMII interface (according to RMII Specification

March 20, 1998). The RMII use a single reference clock (50 MHz) and seven pins which are a proper

subset of the MII interface pins. Ethernet features are unchanged in RMII mode. To select RMII-PHY

interface, a mode bit in the Ethernet mode register (FPSMR) has been added, as shown in Figure 36-6.

Table 36-6. Transmission Errors

Error

Response

Transmitter

underrun

The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the

buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after receiving the

RESTART TRANSMIT

command.

Carrier sense

lost during frame

transmission

If no collision is detected in the frame, the controller sets TxBD[CSL] and FCCE[TXE], and it

continues the buffer transmission normally. No retries are performed as a result of this error.

Retransmission

attempts limit

expired

The controller terminates buffer transmission, closes the buffer, sets TxBD[RL] and FCCE[TXE].

Transmission resumes after receiving the RESTART TRANSMIT command.

Late collision

The controller terminates buffer transmission, closes the buffer, sets TxBD[LC] and FCCE[TXE].

The controller resumes transmission after receiving the RESTART TRANSMIT command. Note that late

collision parameters are defined in FPSMR[LCW].

Table 36-7. Reception Errors

Error

Description

Overrun error

The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer

overrun occurs, the controller writes the received data byte to the internal FIFO buffer over the

previously received byte. The previous data byte and frame status are lost. The controller closes the

buffer, sets RxBD[OV] and FCCE[RXF], and increments the discarded frame counter (DISFC). The

receiver then enters hunt mode.

Busy error

A frame is received and discarded due to a lack of buffers. The controller sets FCCE[BSY] and

increments the discarded frame counter (DISFC).

Non-octet error

(dribbling bits)

The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as

nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC

error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the

alignment error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no

error is reported.

CRC error

When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF].

Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame

with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC

error can be ignored if checking is not required.

MPC8280 Datasheet(PDF) 1253 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1253 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL