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MPC8280 Datasheet(PDF) 1254 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1254 Page - Freescale Semiconductor, Inc

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Fast Ethernet Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
36-20
Freescale Semiconductor
Table 36-8 describes FPSMR fields.
01
23
45
67
89
10
11
12
13
14
15
Field HBC
FC
SBT
LPB
LCW FDE MON
—
PRO
FCE
RSH
—
RMII
—
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x11304 (FPSMR1), 0x11324 (FPSMR2)
16
20
21
22
23
24
25
26
31
Field
—
CAM BRO
—
CRC
—
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2)
Figure 36-6. FCC Ethernet Mode Registers (FPSMR
x)
Table 36-8. FPSMR Ethernet Field Descriptions
Bits
Name
Description
0
HBC
Heartbeat checking
0 No heartbeat checking is performed. Do not wait for a collision after transmission.
1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission.
TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks.
1
FC
Force collision
0 Normal operation
1 The channel forces a collision on transmission of every transmit frame. The MPC8280 should
be configured in loopback operation when using this feature, which allows the user to test the
MPC8280 collision logic. It causes the retry limit to be exceeded for each transmit frame.
2
SBT
Stop backoff timer
0 The backoff timer functions normally.
1 The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is
active. In this method, the retransmission is less aggressive than the maximum allowed in the
IEEE 802.3 standard. The persistence (P_PER) feature in the parameter RAM can be used in
combination with the SBT bit (or in place of the SBT bit).
3
LPB
Local protect bit.
0 Receiver is blocked when transmitter sends (default).
1 Receiver is not blocked when transmitter sends. Must set for full-duplex operation. For external
loopback, GFMR[DIAG] must be programmed also; see Section 30.2, “General FCC Mode
Registers (GFMRx)."
4
LCW
Late collision window
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.
5
FDE
Full duplex Ethernet
0 Disable full-duplex
1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed.
6
MON
RMON mode
0 Disable RMON mode
1 Enable RMON mode



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