MPC8280 datasheet(1264/1386 Pages) FREESCALE

1264 / 1386 page

FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

37-2

Freescale Semiconductor

•

Four address comparison registers with masks

•

Maintenance of four 16-bit error counters

•

Flag/abort/idle generation and detection

•

Zero insertion/deletion

•

16- or 32-bit CRC-CCITT generation/checking

•

Detection of nonoctet-aligned frames

•

Detection of frames that are too long

•

Programmable flags (0–15) between successive frames

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External BD table

•Up to T3 rate

•

Support of time stamp mode for Rx frames

•

Support of nibble mode HDLC (4 bits per clocks)

37.2

HDLC Channel Frame Transmission Processing

The HDLC transmitter is designed to work with almost no core intervention. When the core enables a

transmitter, it starts sending flags or idles as programmed in the HDLC mode register (FPSMR). The

HDLC controller polls the first BD in the transmit channel BD table. When there is a frame to transmit,

the HDLC controller fetches the data (address, control, and information) from the first buffer and begins

sending the frame after first inserting the user-specified minimum number of flags between frames. When

the end of the current buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the

CRC (if selected) and closing flag. In HDLC, the lsb of each octet and the msb of the CRC are sent first.

Figure 37-1 shows a typical HDLC frame.

Figure 37-1. HDLC Framing Structure

After the closing flag is sent, the HDLC controller writes the frame status bits into the BD and clears the

R bit. When the end of the current BD is reached and the L (last) bit is not set (working in multibuffer

mode), only the R bit is cleared. In either mode, an interrupt can be issued if the I bit in the TxBD is set.

The HDLC controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted

after each buffer, after a specific buffer, after each frame, or after a number of frames.

To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT command.

This can be useful for sending expedited data before previously linked buffers or for error situations. When

receiving the STOP TRANSMIT command, the HDLC controller aborts the current frame transmission and

starts transmitting idles or flags. When the HDLC controller is given the RESTART TRANSMIT command, it

resumes transmission. To insert a high-priority frame without aborting the current frame, the GRACEFUL

STOP TRANSMIT

command can be issued. A special interrupt (GRA) can be generated in the event register

when the current frame is complete.

Opening Flag

Address

Control

Information (Optional)

CRC

Closing Flag

8 Bits

16 Bits

8 Bits

n Bits

16 Bits

8 Bits

MPC8280 Datasheet(PDF) 1264 Page - Freescale Semiconductor, Inc

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