MPC8280 datasheet(1339/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

A-1

Appendix A

This section provides a brief guide to the core registers.

A.1

PowerPC Registers—User Registers

The implements the user-level registers defined by the PowerPC architecture except those required for

supporting floating-point operations (the floating-point register file (FPRs) and the floating-point status

and control register (FPSCR)). User-level, PowerPC registers are listed in Table A-1 and Table A-2.

Table A-2 lists user-level special-purpose registers (SPRs).

Table A-2 lists SPRs defined by the PowerPC architecture implemented on the MPC8280.

A.2

PowerPC Registers—Supervisor Registers

All supervisor-level registers implemented on the MPC8280 are SPRs, except for the machine state

Table A-1. User-Level PowerPC Registers (non-SPRs)

Description

Name

Comments

Access Level

Serialize Access

General-purpose

registers

GPRs

The thirty-two 32-bit (GPRs) are used for source

and destination operands.

User

—

Condition register

See the

Programming Environments Manual

User

Only mtcrf

Table A-2. User-Level PowerPC SPRs

SPR Number

Name

Comments

Serialize Access

Decimal SPR [5–9] SPR [0–4]

00000

00001

XER

See the

Programming

Environments Manual

Write: Full sync

Read: Sync relative to load/store operations

00000

01000

See the

Programming

Environments Manual

00000

01001

CTR

See the

Programming

Environments Manual

268

01000

01100

TBL read 1

1 Extended opcode for mftb, 371 rather than 339.

See the

Programming

Environments Manual

Write (as a store)

269

01000

01101

TBU read 2

2 Any write (mtspr) to this address causes an implementation-dependent software emulation exception.

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