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MPC8280 Datasheet(PDF) 1336 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1336 Page - Freescale Semiconductor, Inc

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Parallel I/O Ports
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
41-20
Freescale Semiconductor
41.6
Interrupts from Port C
The port C lines associated with CDx and CTSx have a mode of operation where the pin can be internally
connected to the SCC/FCC but can also generate interrupts. Port C still detects changes on the CTS and
CD pins and asserts the corresponding interrupt request, but the SCC/FCC simultaneously uses CTS
and/or CD to automatically control operation. This lets the user fully implement protocols V.24, X.21, and
X.21 bis (with the assistance of other general-purpose I/O lines).
To configure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates interrupts, these
steps should be followed:
1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0.
2. Write the corresponding PDIRC bit with a zero.
3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause interrupts.
PD8
FCC2: TxPrty 1
UTOPIA
SMC1: SMRXD
GND
BRG5: BRGO
PD7
SMC1: SMSYN
GND
FCC1: TxAddr[3]1,2
MPHY, master,
multiplexed polling
FCC2: TxAddr[4]1
MPHY, master,
multiplexed polling
FCC1: TxAddr[3]1,3
MPHY, slave,
multiplexed polling
FCC1: TxClav21,3
MPHY, master, direct
polling
FCC2: TxAddr[1]1
MPHY, slave,
multiplexed polling
GND
PD6
FCC1: TxD[4] 1
UTOPIA 16
IDMA1: DACK
PD5
FCC1: TxD[3] 1
UTOPIA 16
IDMA1: DONE4
Inout
(secondary option)
VDD
PD4
BRG8: BRGO
TDM_D1:
L1TSYNC/GRANT4
(secondary option)
GND
FCC3: RTS
SMC2: SMRXD4
(secondary option)
GND
1 Not available on the MPC8270.
2 MPHY address pins 3 and 4 (master mode) can come from FCC2, depending on CMXUAR programming. (See
Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”)
3 MPHY address pins 0–4 (slave mode) can come from FCC2, depending on CMXUAR programming. (See
Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”)
4 Available only when the primary option for this function is not used.
Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)
Pin
Pin Function
PSORD = 0
PSORD = 1
PDIRD = 1 (Output)
PDIRD = 0 (Input)
Defaul
t Input
PDIRD = 1 (Output)
PDIRD = 0 (Input, or
Inout if Specified)
Defaul
t Input



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