SN8F27E64KB datasheet(45/192 Pages) SONIX

45 / 192 page

SN8F27E60 Series

8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD

Page 45

Version 1.4

3.2 POWER ON RESET

The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising

curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.



Power-up: System detects the power voltage up and waits for power stable.



External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is

not high level, the system keeps reset status and waits external reset pin released.



System initialization: All system registers is set as initial conditions and system is ready.



Oscillator warm up: Oscillator operation is successfully and supply to system clock.



Program executing: Power on sequence is finished and program executes from ORG 0.

3.3 WATCHDOG RESET

Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.

Under error condition, system is in unknown situation and watchdog can

’t be clear by program before watchdog timer

overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and

returns normal mode. Watchdog reset sequence is as following.



Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the

system is reset.



System initialization: All system registers is set as initial conditions and system is ready.



Oscillator warm up: Oscillator operation is successfully and supply to system clock.



Program executing: Power on sequence is finished and program executes from ORG 0.

Watchdog timer application note is as following.



Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.



Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.



Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the

watchdog timer function.



Note: Please refer to

the “WATCHDOG TIMER” about watchdog timer detail information.

3.4 BROWN OUT RESET

The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external

factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well

or executing program error.

VDD

VSS

System Work

Well Area

System Work

Error Area

Brown Out Reset Diagram

SN8F27E64KB Datasheet(PDF) 45 Page - SONiX Technology Company

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