TMS320C6421 datasheet(6/223 Pages) TI

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Revision History

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS346B device-specific

data manual to make it an SPRS346C revision. Changed C6421 device information to the Production

Data (PD) stage of development.

Scope: Applicable updates to the C642x device family, specifically relating to the TMS320C6421 device,

have been incorporated.

• A 1.05 V core supply voltage is only supported on -6 (600 MHz) devices operating at SYSCLK1 ≤ 400

MHz.

• The C6421 device supports 24-bit SPI Boot (McBSP0 + GP[97]) and VLYNQ Boot.

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Global

•

Updated/Changed L1D RAM from "0-KB" to "16-KB" and modified document where applicable

•

Updated/Changed L1D RAM/Cache from "16-KB" to "32-KB" and modified document where

applicable

•

Added literature references throughout the document.

•

Updated/Changed the following DDR2 pin names:

–

DDR_CLK0 to DDR_CLK

–

DDR_CLK0 to DDR_CLK

–

DDR_BS[0] to DDR_BA[0]

–

DDR_BS[1] to DDR_BA[1]

–

DDR_BS[2] to DDR_BA[2]

•

Updated/Changed the -400, -500, -600 frequency designators from -400, -500, and -600 to -4, -4Q,

-4S, -5, -5Q, -5S, and -6, where "Q" represents automotive and "S" represents automotive (tape and

reel).

•

Updated/Changed the devices that support a 1.05 V core suppply voltage from 400-MHz (-4) devices

to only the 600-MHz (-6) C6421 device when SYSCLK1

≤ 400 MHz.

•

Updated/Changed temperature range designator from "Extended" to "Automotive (Q or S suffix)".

•

Added memory locations to register tables.

Section 1.1

Section 1.1: Added "Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM" to

"32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)" bullet

Section 2.1

Table 2-1, Characteristics of the C6424 Processor

Updated/Changed Product Status from "PP" to "PD"

Section 2.7

Section 2.7, Device and Development-Support Tool Nomenclature:

Updated/Changed example part number from "TMX320C6421AZWTA" to "TMS320C6421ZWTQ6"

Section 2.5

Section 2.5, Terminal Functions

Table 2-17, Host-Port Interface Terminal Functions:

Added "For proper HPI operation, if this pin is routed out, it must be pulled up via an external resistor" to

HAS/MDIO/AD3/GP[83] pin description

Table 2-10, RESET and JTAG Terminal Functions:

Added "For proper device operation, do not oppose the IPU on this pin" statement to TMS pin description

Section 3.1

Section 3.1, System Module Registers

Table 3-1, System Module Register Memory Map:

Updated/Changed EDMATCCFG register Description from "EDMA TC Configuration..." to "EDMA

Transfer Controller Default Burst Size Configuration..."

Section 3.4.1

Section 3.4.1, Boot Modes

Table 3-4 and Table 3-5:

Updated/Changed BOOTMODE[3:0] = 1010 from "Reserved" to "VLYNQ Boot"

Updated/Changed BOOTMODE[3:0] = 1111 from "Reserved" to "24-Bit SPI Boot (McBSP0 + GP[97])"

Section 5.2

Section 5.2, Recommended Operating Conditions:

Updated/Changed DVDD Supply voltage, I/O 3.3V (DVDD33) MIN value from "3.14 V" to "2.97 V"

Updated/Changed DVDD Supply voltage, I/O 3.3V (DVDD33) MAX value from "3.46 V" to "3.63 V"

Added "High-level input voltage, MXI/ CLKIN" with a MIN value of 0.65MXVDD to VIH row

Added "Low-level input voltage, MXI/ CLKIN" with a MAX value of 0.35MXVDD to VIL row

Added table note for CVDD Supply voltage, Core (-6 devices)

Revision History

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