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TMS320C6421 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 223 page  www.ti.com 1 TMS320C6421 Fixed-Point Digital Signal Processor 1.1 Features TMS320C6421 Fixed-Point Digital Signal Processor SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007 • C64x+ L1/L2 Memory Architecture • High-Performance Digital Signal Processor (C6421) – 128K-Bit (16K-Byte) L1P Program RAM/Cache [Flexible Allocation] – 2.5-, 2.-, 1.67-ns Instruction Cycle Time – 384K-Bit (48K-Byte) L1D Data RAM/Cache – 400-, 500-, 600-MHz C64x+™ Clock Rate [Flexible Allocation] – Eight 32-Bit C64x+ Instructions/Cycle – 512K-Bit (64K-Byte) L2 Unified Mapped – 3200, 4000, 4800 MIPS RAM/Cache [Flexible Allocation] – Fully Software-Compatible With C64x • Endianess: Supports Both Little Endian and – Commercial and Automotive (Q or S suffix) Big Endian Grades • External Memory Interfaces (EMIFs) • VelociTI.2™ Extensions to VelociTI™ – 16-Bit DDR2 SDRAM Memory Controller Advanced Very-Long-Instruction-Word (VLIW) With 128M-Byte Address Space (1.8-V I/O) TMS320C64x+™ DSP Core • Supports up to 266-MHz (data rate) bus – Eight Highly Independent Functional Units and interfaces to DDR2-400 SDRAM With VelociTI.2 Extensions: – Asynchronous 8-Bit-Wide EMIF (EMIFA) • Six ALUs (32-/40-Bit), Each Supports With up to 64M-Byte Address Reach Single 32-Bit, Dual 16-Bit, or Quad 8-Bit • Flash Memory Interfaces Arithmetic per Clock Cycle – NOR (8-Bit-Wide Data) • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock – NAND (8-Bit-Wide Data) Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Enhanced Direct-Memory-Access (EDMA) Results) per Clock Cycle Controller (64 Independent Channels) – Load-Store Architecture With Non-Aligned • Two 64-Bit General-Purpose Timers (Each Support Configurable as Two 32-Bit Timers) – 64 32-Bit General-Purpose Registers • One 64-Bit Watch Dog Timer – Instruction Packing Reduces Code Size • One UART With RTS and CTS Flow Control – All Instructions Conditional – Additional C64x+™ Enhancements • Master/Slave Inter-Integrated Circuit (I2C Bus™) • Protected Mode Operation • Exceptions Support for Error Detection • Multichannel Buffered Serial Port (McBSP0) and Program Redirection – I2S and TDM • Hardware Support for Modulo Loop – AC97 Audio Codec Interface Auto-Focus Module Operation – SPI • C64x+ Instruction Set Features – Standard Voice Codec Interface (AIC12) – Byte-Addressable (8-/16-/32-/64-Bit Data) – Telecom Interfaces – ST-Bus, H-100 – 8-Bit Overflow Protection – 128 Channel Mode – Bit-Field Extract, Set, Clear • Multichannel Audio Serial Port (McASP0) – Normalization, Saturation, Bit-Counting – Four Serializers and SPDIF (DIT) Mode – VelociTI.2 Increased Orthogonality • 16-Bit Host-Port Interface (HPI) – C64x+ Extensions • 10/100 Mb/s Ethernet MAC (EMAC) • Compact 16-bit Instructions – IEEE 802.3 Compliant • Additional Instructions to Support – Supports Multiple Media Independent Complex Multiplies Interfaces (MII, RMII) – Management Data I/O (MDIO) Module Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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