ADRV9002BBCZ datasheet(93/100 Pages) AD

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Data Sheet

ADRV9002

THEORY OF OPERATION

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Rev. A | 93 of 100

RECEIVER

Figure 361 shows a simplified block diagram of the ADRV9002

receiver. It is a fully integrated, direct conversion, low IF receiver

signal chain. The receiver subsystem consists of a resistive input

network for gain control followed by a current mode passive mixer.

The output current of the mixer is converted to a voltage by a

transimpedance amplifier and then digitized. There are two sets of

ADCs, a high performance Σ-Δ ADC and a low power ADC. The

digital baseband that provides the required filtering and decimation

follows these ADCs.

There are two RF inputs for each receiver to match different

bands in one reference design. The mixer architecture is linear and

inherently wideband, which facilitates impedance matching. The

differential input impedance of the receiver inputs is 100 Ω.

To achieve gain control, a programmed gain index map is imple-

mented. This gain map distributes attenuation among the various

receiver blocks for optimal performance at each power level. The

gain range is 34 dB. Additional support is available for both auto-

matic and manual gain control modes.

The receive LPFs can be reconfigured to help provide antialias

filtering and improve out of band blockers. The ADRV9002 is a

wideband architecture transceiver that relies on the ADC high

dynamic range to receive signals and interference at the same

time. Filtering provided by the receive LPF attenuates ADC alias

images. The receive LPF characteristic is flat and not intended to

provide rejection of close in blockers. The baseband filter supports

a baseband bandwidth from 5 MHz to 50 MHz.

The receiver includes two ADC pairs. One pair consists of high per-

formance Σ-Δ ADCs to provide maximum interferer tolerance, and

the second pair consists of ADCs for significant power reduction.

The extra pair of ADCs allow a smart trade-off between power and

performance.

The ADC output can be conditioned further by a series of deci-

mation filters and a fully programmable, 128-tap FIR filter with

additional decimation settings. The sample rate of each digital filter

block automatically adjusts with each change of the decimation

factors to produce the desired output data rate.

For standards that demand low phase noise performance, the

ADRV9002 can operate in low IF mode. The ADRV9002 can re-

ceive signals offset from the carrier, as with an IF downconversion

scheme. A digital NCO and mixer that follow the analog receive

path can downconvert the IF signal to baseband. Downconverting

the signal to baseband allows a lower sample rate on the data bus.

The ADRV9002 makes no assumptions about high-side or low-side

injection.

Monitor Mode

The ADRV9002 receiver signal chain can be configured to monitor

the radio channel signal level in duty cycle detection and sleep

fashion. Monitor mode allows the digital baseband processor to

power down until the ADRV9002 detects a signal. Monitor mode

provides overall system power saving. The timing of detection and

sleep mode is fully programmable. Alternatively, the ADRV9002

can be under full control of the baseband processor during monitor

mode.

Figure 361. Receiver Architecture

ADRV9002BBCZ Datasheet(PDF) 93 Page - Analog Devices

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