ADRV9002BBCZ datasheet(94/100 Pages) AD

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Data Sheet

ADRV9002

THEORY OF OPERATION

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Rev. A | 94 of 100

DPD

The ADRV9002 provides a fully integrated DPD function that alters

the digital waveform to compensate for nonlinearities in the power

amplifier response, which linearizes the output of the power amplifi-

er of the transmit system. The internal DPD block is optimized for

both narrow-band and wideband signals. The DPD actuator and

coefficient calculation engine are both integrated. This functionality

uses the receive channel to monitor the output of the power am-

plifier and calculates the appropriate predistortion to linearize the

output. The integrated DPD capability allows the system to drive

the power amplifier closer to saturation, enabling a higher efficiency

power amplifier while maintaining linearity.

Receiver as an Observation Receiver

In FDD type applications where only one receiver is used or in

the TDD type applications during transmitter time slots, unused

receiver inputs can be used to perform transmitter observation.

The observation receiver operates in a similar manner to the main

receivers.

Use the observation receiver channel to perform the following:

►

Monitor the transmitter channels and implement transmitter local

oscillator leakage (LOL) correction and transmitter QEC.

►

Monitor signal levels after the power amplifier output. This data

can be used by a fully integrated low power DPD block. The

integrated DPD is optimized for both narrow-band and wideband

signals and enables linearization of high efficiency power amplifi-

ers.

►

Monitor signal levels after the power amplifier output for further

data processing in the external baseband processor.

In cases where the observation receiver path is used for DPD oper-

ation, there is a limit to the maximum bandwidth of the transmitter

signal the DPD can support. For example, if the DPD observation

factor is 5×, the transmitter signal bandwidth is limited to 1/5 of the

DPD observation bandwidth. When using the ADRV9002 internal

DPD block, the largest transmitter bandwidth that the internal DPD

can support is 20 MHz because of the largest internal DPD obser-

vation bandwidth of 100 MHz. When external DPD is used, the

largest DPD observation bandwidth is limited by the transmitter and

observation receiver RF bandwidth. 40 MHz is the largest RF band-

width that can be received and sent over the digital data port to

the baseband processor, which implies that 8 MHz represents the

largest transmitter bandwidth that the DPD implemented externally

to the ADRV9002 can support.

CLOCK INPUT

The reference clock inputs provide a low frequency clock from

which all internal ADRV9002 clocks are derived. The ADRV9002

offers multiple reference input clocking options. The reference input

clock pins on the device are labeled DEV_CLK_IN±.

For optimal performance, drive the reference clock differentially via

an external source or from an external crystal. If a differential input

clock is provided, the clock signal must be ac-coupled with the input

range limited from 10 MHz to 1 GHz. The ADRV9002 can also

accept an external crystal (XTAL) as a clock source. The frequency

range of the supported crystal is between 20 MHz to 80 MHz. The

external crystal connection must be dc-coupled.

If a differential clock is not available, a single-ended, ac-cou-

pled, 1 V p-p (maximum) CMOS signal can be applied to the

DEV_CLK_IN+ pin with the DEV_CLK_IN− pin unconnected. The

maximum clock frequency in this mode is limited to 80 MHz.

SYNTHESIZERS

The ADRV9002 offers two distinct PLL paths, an RF PLL for the

high frequency RF path and a baseband PLL for the digital and

sampling clocks of the data converters.

RF PLL

The PLL structure in the ADRV9002 is unique in the sense that

instead of having one dedicated PLL for the receive data path and

a dedicated PLL for the transmit data path, two RF PLLs are in the

device and both PLLs can source the receiver, the transmitter, both

paths, or neither. This flexibility enables the ADRV9002 to meet

various applications that require versatility.

The RF PLL supports the use of both internal and external LO

signals. The internal LO is generated by an on-chip VCO, which is

tunable over a frequency range of 6.5 GHz to 13 GHz. The output

of the VCO is phase-locked to an external reference clock through

a fractional-N PLL that is programmable through the API command.

The VCO outputs are steered through a combination of frequency

dividers to produce in-phase and quadrature phase LO signals in

the 30 MHz to 6 GHz frequency range.

Alternatively, an external LO signal can be applied to the external

LO inputs of the ADRV9002 to generate the LO signals in quadra-

ture for the RF path. If the external LO path is chosen, the input

frequency range is between 60 MHz and 12 GHz.

PLL synthesizers are fractional-N designs that incorporate com-

pletely integrated VCOs and loop filters. In TDD mode, LO distri-

bution paths and receive and transmit data paths turn on and

off as appropriate for the receive and transmit frames. In FDD

mode, the transmit PLL and the receive PLL can be activated

simultaneously. These PLLs require no external components. The

RF LO generation circuits offer a trade-off between performance

and power consumption.

ADRV9002BBCZ Datasheet(PDF) 94 Page - Analog Devices

ADRV9002BBCZ Datasheet(HTML) 94 Page - Analog Devices

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