ADRV9002BBCZ datasheet(24/100 Pages) AD

24 / 100 page

Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 24 of 100

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

Input

VTX2LO_1P3

1.3 V Supply for Tx2 LO Buffers, Upconverter, and LO Delay. Provide a 1.0 V supply to VTX2LO_1P3

when the internal LDO is not used. VTX2LO_1P3 is sensitive to supply noise.

Input

VCLKVCO_1P3

1.3 V Internal LDO Input Supply for Clock LO VCO and LO Generation Circuitry. VCLKVCO_1P3 is

sensitive to supply noise.

Input

VCONV_1P8

1.8 V Supply for Tx1 and Tx2 DAC and Rx1 and Rx2 ADC.

Input

VAGPIO_1P8

1.8 V Supply for Auxiliary DACs, Auxiliary ADCs, and AGPIO Signals.

G10

Input

VAUXVCO_1P3

1.3 V Internal LDO Input Supply for Auxiliary LO VCO and LO Generation Circuitry. VAUXVCO_1P3 is

sensitive to supply noise.

G12

Input

VTX1LO_1P3

1.3 V Internal LDO Input Supply for Tx1 LO Buffers, Upconverter, and LO Delay. Provide a 1.0 V supply

to VTX1LO_1P3 when the internal LDO regulator is not used. VTX1LO_1P3 is sensitive to supply noise.

G14, H14

Output

TX1+, TX1−

Differential Output for Transmitter Channel 1. If unused, do not connect TX1+ and TX1−.

Input

VANA2_1P8

1.8 V Supply for Rx2 Mixer, Rx2 TIA, Tx2 LPF, and Internal References.

Output

VTX2LO_1P0

1.0 V Internal Supply Node for Tx2 LO Buffers, Upconverter, and LO Delay. For normal operation, leave

VTX2LO_1P0 unconnected.

Input

AUXADC_3

Input 3 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_3.

Output

VCLKVCO_1P0

1.0 V Internal Supply Node for Clock LO VCO and LO Generation Circuitry. Bypass VCLKVCO_1P0 with

a 4.7 µF capacitor.

Output

VCONV_1P0

1.0 V Internal Supply Node for Receiver ADCs and Transmitter DACs. Bypass VCONV_1P0 with a 4.7

µF capacitor.

Input

VCONV_1P3

1.3 V Internal LDO Input Supply for Receiver ADCs and Transmitter DACs. Provide a 1.0 V supply to

VCONV_1P3 when the internal LDO regulator is not used. VCONV_1P3 is sensitive to supply noise.

H10

Output

VAUXVCO_1P0

1.0 V Internal Supply Node for Auxiliary LO VCO and LO Generation Circuitry. Bypass VAUXVCO_1P0

with a 4.7 µF Capacitor.

H11

Input

AUXADC_0

Input 0 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_0.

H12

Output

VTX1LO_1P0

1.0 V Internal Supply Node for Tx1 LO Buffers, Upconverter, and LO Delay. For normal operation, leave

VTX1LO_1P0 unconnected.

H13

Input

VANA1_1P8

1.8 V Supply for Rx1 Mixer, Rx1 TIA, Tx1 LPF, Crystal Oscillator, DEV_CLK Circuitry, and Internal

References.

Input

SPI_CLK

Serial Data Bus Clock Input.

Input and

Output

SPI_DIO

Serial Data Input in 4-Wire Mode or Input and Output in 3-Wire Mode.

Input

RX2_EN

Enable Input for Rx2. If unused, do not connect RX2_EN.

Input

VSSA/TESTCK+

Connect VSSA/TESTCK+ to VSSA for normal operation.

Input

VSSA/TESTCK−

Connect VSSA/TESTCK− to VSSA for normal operation.

K6 to K11, L4 to L6, L9 to L11

Input and

Output

DGPIO_xx

Digital GPIO. VDIGIO_1P8 supplies 1.8 V to DGPIO_xx. See Table 18 to match the pin location to the

DGPIO_xx signal name. If unused, do not connect DGPIO_xx.

K12

Input

RX1_EN

Enable Input for Rx1. If unused, do not connect RX1_EN.

K13

Input

RESETB

Active Low Chip Reset.

K14

Output

GP_INT

General-Purpose Digital Interrupt Output Signal. If unused, do not connect GP_INT.

Input

SPI_EN

Active Low Serial Data Bus Chip Select.

Output

SPI_DO

Serial Data Output. If unused in SPI 3-wire mode, do not connect SPI_DO.

Input

TX2_EN

Enable Input for Transmitter Channel 2. If unused, do not connect TX2_EN.

L7, L8

Input

VDIG_1P0

1.0 V Digital Core. Connect Pin L7 and Pin L8 together. Use a wide trace to connect the VDIG_1P0 pins

to a separate power supply domain. Provide reservoir capacitance close to the chip.

L12

Input

TX1_EN

Enable Input for Transmitter Channel 1. If unused, do not connect TX1_EN.

L13

Input

MODE

Joint Test Action Group (JTAG) Boundary Scan Pin. See Table 19 for more information. If unused,

connect MODE to VSSA.

L14

Output

DEV_CLK_OUT

Single-Ended Device Clock Output. DEV_CLK_OUT provides a DEV_CLK signal or the divided version

to the baseband IC. If unused, do not connect DEV_CLK_OUT.

ADRV9002BBCZ Datasheet(PDF) 24 Page - Analog Devices

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