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ADRV9002BBCZ Datasheet(PDF) 98 Page - Analog Devices |
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ADRV9002BBCZ Datasheet(HTML) 98 Page - Analog Devices |
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98 / 100 page ![]() Data Sheet ADRV9002 APPLICATIONS INFORMATION analog.com Rev. A | 98 of 100 Table 20. ADRV9002 Data Port Interface Modes Interface Mode Data Lanes per Channel Serialization Factor per Data Lane Maximum Data Lane Rate (MHz) Maximum Clock Rate (MHz) Maximum RF Bandwidth (MHz) Sample Rate for I and Q Data (MHz) Data Type1 Figure Reference CSSI in 1-Lane Data 1 32 80 80 1.25 2.5 Normal Figure 363 CSSI in 1-Lane Data 1 32 160 80 2.5 5 DDR CSSI in 4-Lane Data 4 8 80 80 5 10 Normal CSSI in 4-Lane Data 4 8 160 80 10 20 DDR Figure 364 LSSI in 1-Lane Data 1 32 983.04 491.52 20 30.72 DDR LSSI in 2-Lane Data 2 16 983.04 491.52 40 61.44 DDR Figure 365 LSSI in 2-Lane Data 2 12 737.28 368.64 40 61.44 DDR 1 Normal data type refers to data on the rising edges, and DDR is double data rate, where data is available on the rising and falling edges of the input clock. Figure 363. CSSI in 1-Lane Data Mode |
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