FS32K142HAT0MLHT datasheet(15/84 Pages) NXP

15 / 84 page

Table 5. VDD supply LVR, LVD and POR operating requirements (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

VLVW

Falling low-voltage warning threshold

4.19

4.305

4.5

VLVW_HYST

LVW hysteresis

—

VBG

Bandgap voltage reference

0.97

1.00

1.03

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

4.6 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration:

• RUN Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• HSRUN Mode:

• Clock source: SPLL

• SYS_CLK/CORE_CLK = 112 MHz

• BUS_CLK = 56 MHz

• FLASH_CLK = 28 MHz

• VLPR Mode:

• Clock source: SIRC

• SYS_CLK/CORE_CLK = 4 MHz

• BUS_CLK = 4 MHz

• FLASH_CLK = 1 MHz

• STOP1/STOP2 Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• VLPS Mode: All clock sources disabled 1

Table 6. Power mode transition operating behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

tPOR

After a POR event, amount of time from the point VDD

reaches 2.7 V to execution of the first instruction

across the operating temperature range of the chip.

—

325

—

μs

Table continues on the next page...

• For S32K11x – FIRC/SOSC

• For S32K14x – FIRC/SOSC/SPLL

General

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

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