FS32K142HAT0MLHT datasheet(23/84 Pages) NXP

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I/O parameters

5.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

Figure 7. Input signal measurement reference

5.2 General AC specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 10. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous path

—

WFRST

RESET input filtered pulse

—

WNFRST

RESET input not filtered pulse

Maximum of

(100 ns, bus

clock period)

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in

that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.

4. Maximum length of RESET pulse which will be the filtered by internal filter only if PCR_PTA5[PFE] is at its reset value of

1'b1.

5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter only if PCR_PTA5[PFE] is at its reset

value of 1'b1. This number depends on the bus clock period also. In this case, minimum pulse width which will cause reset

is 250 ns. For faster clock frequencies which have clock period less than 100 ns, the minimum pulse width not filtered will

I/O parameters

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

FS32K142HAT0MLHT Datasheet(PDF) 23 Page - NXP Semiconductors

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