FS32K142HAT0MLHT datasheet(33/84 Pages) NXP

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6.2.4 Low Power Oscillator (LPO) electrical specifications

Table 21. Low Power Oscillator (LPO) electrical specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

FLPO

Internal low power oscillator frequency

113

128

139

kHz

Tstartup

Startup Time

—

µs

6.2.5 SPLL electrical specifications

Table 22. SPLL electrical specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

FSPLL_REF1 PLL Reference Frequency Range

—

MHz

FSPLL_Input2 PLL Input Frequency

—

MHz

FVCO_CLK

VCO output frequency

180

—

320

MHz

FSPLL_CLK

PLL output frequency

—

160

MHz

JCYC_SPLL

PLL Period Jitter (RMS)3

at FVCO_CLK 180 MHz

—

120

—

at FVCO_CLK 320 MHz

—

JACC_SPLL

PLL accumulated jitter over 1µs (RMS)3

at FVCO_CLK 180 MHz

—

1350

—

at FVCO_CLK 320 MHz

—

600

—

DUNL

Lock exit frequency tolerance

± 4.47

—

± 5.97

TSPLL_LOCK Lock detector detection time4

—

150 × 10-6 +

1075(1/FSPLL_REF)

1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG

2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input

source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass

mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.

3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each

PCB and results will vary

4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.

Memory and memory interfaces

6.3.1 Flash memory module (FTFC) electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.3

Memory and memory interfaces

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

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