FS32K142HAT0MLHT datasheet(45/84 Pages) NXP

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6.4.1.2 12-bit ADC electrical characteristics

NOTE

• ADC performance specifications are documented using a

single ADC. For parallel/simultaneous operation of both

ADCs, either for sampling the same channel by both ADCs

or for sampling different channels by each ADC, some

amount of decrease in performance can be expected. Care

must be taken to stagger the two ADC conversions, in

particular the sample phase, to minimize the impact of

simultaneous conversions.

• On reduced pin packages where ADC reference pins are

shared with supply pins, ADC analog performance

characteristics may be impacted. The amount of variation

will be directly impacted by the external PCB layout and

hence care must be taken with PCB routing. See AN5426

for details

Table 28. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS)

Symbol

Description

Conditions 1

Min.

Typ.2

Max.

Unit

Notes

VDDA

Supply voltage

2.7

—

IDDA_ADC Supply current per ADC

—

0.6

—

SMPLTS Sample Time

275

—

Refer to

the

Reference

Manual

TUE4

Total unadjusted error

—

±4

±8

LSB5

6, 7, 8, 9

DNL

Differential non-linearity

—

±1.0

—

LSB5

6, 7, 8, 9

INL

Integral non-linearity

—

±2.0

—

LSB5

6, 7, 8, 9

1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than

or equal to half of the maximum specified ADC clock frequency.

2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.

3. The ADC supply current depends on the ADC conversion rate.

4. Represents total static error, which includes offset and full scale error.

5. 1 LSB = (VREFH - VREFL)/2N

6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device

use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings

for AVGS.

7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

9. All the parameters in the table are given assuming system clock as the clocking source for ADC.

ADC electrical specifications

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

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