PIC24FJ1024GA606 datasheet(2/466 Pages) MICROCHIP

2 / 466 page

PIC24FJ1024GA610/GB610 FAMILY

DS30010074C-page 2

 2015 Microchip Technology Inc.

Peripheral Features

• Peripheral Pin Select (PPS) –Allows Independent

I/O Mapping of Many Peripherals

• Up to 5 External Interrupt Sources

• Configurable Interrupt-on-Change on All I/O Pins:

- Each pin is independently configurable for rising

edge or falling edge change detection

• Eight-Channel DMA Supports All Peripheral modules:

- Minimizes CPU overhead and increases data

throughput

• Five 16-Bit Timers/Counters with Prescalers:

- Can be paired as 32-bit timers/counters

• Six Input Capture modules, Each with a Dedicated

16-Bit Timer

• Six Output Compare/PWM modules, Each with a

Dedicated 16-Bit Timer

• Four Single Output CCPs (SCCPs) and Three

Multiple Output CCPs (MCCPs):

- Independent 16/32-bit time base for each module

- Internal time base and period registers

- Legacy PIC24F Capture and Compare modes

(16 and 32-bit)

- Special Variable Frequency Pulse and Brushless

DC Motor Output modes

• Enhanced Parallel Master/Slave Port (EPMP/EPSP)

• Hardware Real-Time Clock/Calendar (RTCC) with

Timestamping

• Three 3-Wire/4-Wire SPI modules:

- Support 4 Frame modes

- 8-level FIFO buffer

- Support I2S operation

•Three I2C modules Support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing

• Six UART modules:

- Support RS-485, RS-232 and LIN/J2602

- On-chip hardware encoder/decoder for IrDA®

- Auto-wake-up on Auto-Baud Detect (ABD)

- 4-level deep FIFO buffer

• Programmable 32-Bit Cyclic Redundancy Check

(CRC) Generator

• Four Configurable Logic Cells (CLCs):

- Two inputs and one output, all mappable to

peripherals or I/O pins

- AND/OR/XOR logic and D/JK flip-flop functions

• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

• Configurable Open-Drain Outputs on Digital I/O Pins

• 5.5V Tolerant Inputs on Multiple I/O Pins

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