PIC24FJ1024GA606 datasheet(53/466 Pages) MICROCHIP

53 / 466 page

 2015 Microchip Technology Inc.

DS30010074C-page 53

PIC24FJ1024GA610/GB610 FAMILY

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and buses. This architecture also allows direct

access of program memory from the Data Space during

code execution.

4.1

Program Memory Space

The program address memory space of the

PIC24FJ1024GA610/GB610 family devices is 4M

instructions. The space is addressable by a 24-bit value

derived from either the 23-bit Program Counter (PC)

during program execution, or from table operation or

Data Space remapping, as described in Section 4.3

“Interfacing Program and Data Memory Spaces”

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and customer OTP sections of

the configuration memory space.

The PIC24FJ1024GA610/GB610 family of devices

supports a Single Partition mode and two Dual Partition

modes. The Dual Partition modes allow the device to

be programmed with two separate applications to facil-

itate bootloading or to allow an application to be

programmed at run time without stalling the CPU.

Memory maps for the PIC24FJ1024GA610/GB610

family of devices are shown in Figure 4-1.

PIC24FJ1024GA606 Datasheet(PDF) 53 Page - Microchip Technology