STM32L4S5AI datasheet(238/275 Pages) STMICROELECTRONICS

238 / 275 page

Electrical characteristics

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

238/275

DocID030322 Rev 2

NAND controller waveforms and timings

Figure 52 through Figure 55 represent synchronous waveforms, and Table 109 and

Table 110 provide the corresponding timings. The results shown in these tables are

obtained with the following FMC configuration:

•

COM.FMC_SetupTime = 0x01

•

COM.FMC_WaitSetupTime = 0x03

•

COM.FMC_HoldSetupTime = 0x02

•

COM.FMC_HiZSetupTime = 0x01

•

ATT.FMC_SetupTime = 0x01

•

ATT.FMC_WaitSetupTime = 0x03

•

ATT.FMC_HoldSetupTime = 0x02

•

ATT.FMC_HiZSetupTime = 0x01

•

Bank = FMC_Bank_NAND

•

MemoryDataWidth = FMC_MemoryDataWidth_16b

•

ECC = FMC_ECC_Enable

•

ECCPageSize = FMC_ECCPageSize_512Bytes

•

TCLRSetupTime = 0

•

TARSetupTime = 0

In all timing tables, the THCLK is the HCLK clock period.

Table 108. Synchronous non-multiplexed PSRAM write timings(1)(2)(3)

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FMC_CLK period

RxTHCLK-0.5

td(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x=0..2)

2.5

td(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x= 0…2)

RxTHCLK/2 +1

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low

2.5

td(CLKL-NADVH) FMC_CLK low to FMC_NADV high

td(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x=16…25)

5.5

td(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x=16…25)

RxTHCLK/2 +0.5

td(CLKL-NWEL)

FMC_CLK low to FMC_NWE low

td(CLKH-NWEH)

FMC_CLK high to FMC_NWE high

RxTHCLK/2 +1

td(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK low

3.5

td(CLKL-NBLL)

FMC_CLK low to FMC_NBL low

td(CLKH-NBLH)

FMC_CLK high to FMC_NBL high

RxTHCLK/2 +1.5

tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high

1.5

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

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