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STM32L4S5AI Datasheet(PDF) 246 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 246 Page - STMicroelectronics |
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246 / 275 page ![]() Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 246/275 DocID030322 Rev 2 6.3.33 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 114 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 21, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data format: 14 bits • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 x VDD Figure 61. DCMI timing diagram Table 114. DCMI characteristics(1) Symbol Parameter Condition Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK -- 0.4 - DCMI_PIXCLK Pixel clock input 1.71 < VDD < 3.6 Voltage range V1 -48 MHz 1.71 < VDD < 3.6 Voltage range V2 -10 Dpixel Pixel clock input duty cycle - 30 70 % MS32414V2 DCMI_PIXCLK tsu(VSYNC) tsu(HSYNC) DCMI_HSYNC DCMI_VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) |
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