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STM32L4S5AI Datasheet(PDF) 248 Page - STMicroelectronics

Part # STM32L4S5AI
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AESHASH
PDF  275 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4S5AI Datasheet(HTML) 248 Page - STMicroelectronics

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Electrical characteristics
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
248/275
DocID030322 Rev 2
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
6.3.35
SD/SDIO/MMC card host interfaces (SDMMC)
Unless otherwise specified, the parameters given in Table xx for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 22: General operating conditions with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 6.3.17: I/O
port characteristics for more details on the input/output characteristics.
Table 115. LTDC characteristics(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Conditions
Min
Max
Unit
fCLK
DCLK
LTDC clock output
frequency
2.7 V < VDD < 3.6 V
-
83
MHz
1.71 V < VDD < 3.6 V
-
50
LTDC clock output duty
cycle
-45
55
%
tw(CLKH)
tw(CLKL)
Clock high time
Clock low time
-
tw(CLK)/2-0.5 tw(CLK)/2+0.5
-
tv(DATA)
Data output valid time
-
-
6
th(DATA)
Data output hold time
-
0
-
tv(HSYNC)
tv(VSYNC)
tv(DE)
HSYNC/VSYNC/DE
output valid time
--
3
th(HSYNC)
th(VSYNC)
th(DE)
HSYNC/VSYNC/DE
output hold time
-0
-
Table 116. Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer
mode
-0
-
66
MHz
-
SDIO_CK/fPCLK2 frequency
ratio
--
-
8/3
-
tW(CKL)
Clock low time
fpp = 52 MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
fpp = 52 MHz
8.5
9.5
-



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