ADC0820-N

SNAS529C – JUNE 1999 – REVISED MARCH 2013

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Figure 18. Sampled-Data Comparator

Figure 19. ADC0820-N Comparator (from MS Flash

ADC)

ARCHITECTURE

In the ADC0820-N, one bank of 15 comparators is used in each 4-bit flash A/D converter (Figure 25). The MS

(most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of

comparators operate alternately, with one group in its zeroing cycle while the other is comparing.

When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from

zeroing to comparison mode (Figure 24). When WR is returned high after at least 600 ns, the output from the

first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change

modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600 ns later, the RD line

may be pulled low to latch the lower 4 data bits and finish the 8-bit conversion. When RD goes low, the flash

A/Ds change state once again in preparation for the next conversion.

Figure 24 also outlines how the converter's interface timing relates to its analog input (VIN). In WR-RD mode, VIN

is measured while WR is low. In RD mode, sampling occurs during the first 800 ns of RD. Because of the input

connections to the ADC0820-N's LS and MS comparators, the converter has the ability to sample VIN at one

instant (see Inherent Sample-Hold), despite the fact that two separate 4-bit conversions are being done. More

specifically, when WR is low the MS flash is in compare mode (connected to VIN), and the LS flash is in zero

mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time.

DIGITAL INTERFACE

The ADC0820-N has two basic interface modes which are selected by strapping the MODE pin high or low.

RD Mode

With the MODE pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is

done by pulling RD low until output data appears. An INT line is provided which goes low at the end of the

conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can

also serve as a system Transfer Acknowledge signal.

Figure 20. RD Mode (Pin 7 is Low)

When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash

converter goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns,

data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800 ns, the

lower 4 bits are recovered.

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