MB85AS12MT

DS501-00071-1v1-E

7



RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input

to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the

RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising

of CS.



WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR

op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR

command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register cannot be written. The SI

value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command,

and do not change the WP signal level until the end of command sequence.

After rising edge of CS, MB85AS12MT starts writing operation to nonvolatile register and set WIP bit in status

register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR

command is executable for WIP polling during this writing process, any other commands will not be per-

formed.

SO

SCK

SI

CS

00000101

High-Z

7

6

5

4

3

2

1

0

Invalid

MSB

7

6

5

4

3

2

1

0

Data Out

LSB

Invalid

SO

SCK

SI

CS

00000001

7

6

5

4

3

2

1

0

Data In

MSB

7

6

5

4

3

2

1

0

High-Z

LSB

7654

3

210

Instruction