BQ25713 datasheet(32/94 Pages) TI2

32 / 94 page

9.4.2 USB On-The-Go

BQ25713/BQ25713B supports USB OTG functionality to deliver power from the battery to other portable devices

through USB port (reverse mode). The OTG output voltage is compliant with USB PD specification, including 5

V, 9 V, 15 V, and 20 V. The output current regulation is compliant with USB type C specification, including 500

mA, 1.5 A, 3 A and 5 A.

Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve

efficiency.

9.4.3 Pass Through Mode (PTM)

When the system is in the sleep mode or light load condition, the charger can be operated in the pass through

mode to improve the light load efficiency. In TI patented pass through mode (PTM), the Buck and Boost high

side FETs are both turned on, while the Buck and Boost low side FETs are both turned off. The input power is

directly passed through the charger to the system. The switching losses of MOSFETs and the inductor core loss

are saved.

Device will be transition from normal Buck-Boost operation to PTM operation by:

• Set REG0x32[7] = 0, to disable the EN_EXITILIM.

• Set REG0x31[0] = 1.

• Set REG0x30[2] = 1.

• Ground ILIM_HIZ pin.

Device will transition out of PTM mode with host control by:

• Set REG0x30[2] = 0.

• Pull ILIM_HIZ pin to high.

• Device exits PTM to buck-boost operation if tripping VINDPM.

• Device exits PTM to buck-boost operation under fault conditions

9.5 Programming

The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as

summarized in Section 9.5.1. The I2C address is D6h. The ManufacturerID and DeviceID registers are assigned

identify the charger device. The ManufacturerID register command always returns 40h.

9.5.1 I2C Serial Interface

The BQ25713/BQ25713B uses I2C compatible interface for flexible charging parameter programming and

instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two bus lines are

required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves

when performing data transfers. A master is the device which initiates a data transfer on the bus and generates

the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address D6h, receiving control inputs from the master device like

micro controller or a digital signal processor through REG00-REG3A. The I2C interface supports both standard

mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current

source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

9.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

BQ25713, BQ25713B

SLUSD83C – JUNE 2018 – REVISED MAY 2023

www.ti.com

Submit Document Feedback

Product Folder Links: BQ25713 BQ25713B

BQ25713 Datasheet(PDF) 32 Page - Texas Instruments

BQ25713 Datasheet(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL