DAC80504 datasheet(22/50 Pages) TI2

22 / 50 page

DAC80504, DAC70504, DAC60504

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

www.ti.com

Product Folder Links: DAC80504 DAC70504 DAC60504

Submit Documentation Feedback

Feature Description (continued)

8.3.1.2 Output Amplifiers

The DACx0504 output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a

maximum output range of 0 V to VDD. Each buffer amplifier is capable of driving a load of 2 kΩ in parallel with

10 nF to GND.

The full-scale output voltage for each channel is determined by the reference voltage (VREF), the reference

divider setting (DIV), and the output buffer gain for that channel (GAIN), as shown in Table 1. After a power-up or

reset event the DIV and GAIN settings are set by the REFDIV and GAIN pins, respectively. During normal

operation the DIV and GAIN settings can be reconfigured through the REF-DIV and BUFF-GAIN bit (see

Equation 1). The GAIN setting for each output channel can be individually configured thus enabling independent

output voltage ranges for each DAC output.

Table 1. DAC Output Range Configuration

DIV SETTING

GAIN SETTING

DAC OUTPUT RANGE

÷2

×1

0 V to ½ × VREF

÷1

×1

Not recommended

÷2

×2

0 V to VREF

÷1

×2

0 V to 2 × VREF

8.3.1.3 DAC Register Structure

Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the

DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)

or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC

outputs change to their new values. When the host reads from a DAC Data register, the value held in the DAC

buffer register is returned (not the value held in the DAC active register).

8.3.1.3.1

DAC Register Synchronous and Asynchronous Updates

The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In

asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register

and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not

automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC

trigger is generated either through the LDAC bit in the TRIGGER register or by the LDAC pin. The synchronous

update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time

of 1 µs is required between DAC output updates.

8.3.1.3.2

Broadcast DAC Register

The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a

single register write. Each DAC channel can be configured to update or remain unaffected by a broadcast

command by setting the corresponding DAC-BRDCAST-EN bit in the SYNC register. A register write to the

BRDCAST-DATA register forces those DAC channels that have been configured for broadcast operation to

update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their

synchronous mode configuration.

DAC80504 Datasheet(PDF) 22 Page - Texas Instruments

DAC80504 Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL