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DAC80504, DAC70504, DAC60504

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

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Product Folder Links: DAC80504 DAC70504 DAC60504

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Copyright © 2017–2019, Texas Instruments Incorporated

(1)

All input signals are specified at tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH) / 2, VDD = 2.7 V to 5.5 V,

VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)

8.5 Programming

The DACx0504 is controlled through a flexible four-wire serial interface that is compatible with SPI type

interfaces used on many microcontrollers and DSP controllers. The interface provides read and write access to

all DACx0504 registers and can also be configured to daisy-chain multiple devices for write operations. The

DACx0504 incorporates an optional error checking mode to validate SPI data communication integrity in noisy

environments. Table 7 shows the SPI timing requirements. Figure 62 and Figure 63 show the SPI write and read

timing diagrams, respectively. Figure 64 shows the digital logic timing diagram.

Table 7. Programming Timing Requirements(1)

VIO = 1.7 V to 2.7 V

VIO = 2.7 V to 5.5 V

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

SERIAL INTERFACE – WRITE OPERATION

fSCLK

SCLK frequency

50

50

MHz

tSCLKHIGH

SCLK high time

9

9

ns

tSCLKLOW

SCLK low time

9

9

ns

tSDIS

SDI setup

5

5

ns

tSDIH

SDI hold

10

10

ns

tCSS

CS to SCLK falling edge setup

13

13

ns

tCSH

SCLK falling edge to CS rising edge

10

10

ns

tCSHIGH

CS high time

15

15

ns

tCSIGNORE

SCLK falling edge to CS ignore

7

7

ns

SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0

fSCLK

SCLK frequency

12

18

MHz

tSCLKHIGH

SCLK high time

35

25

ns

tSCLKLOW

SCLK low time

35

25

ns

tSDIS

SDI setup

5

5

ns

tSDIH

SDI hold

10

10

ns

tCSS

CS to SCLK falling edge setup

32

20

ns

tCSH

SCLK falling edge to CS rising edge

10

10

ns

tCSHIGH

CS high time

15

15

ns

tSDODLY

SDO output delay from SCLK rising edge

3.5

33.5

3.5

23

ns

tSDODZ

SDO driven to tri-state

0

30

0

25

ns

tCSIGNORE

SCLK falling edge to CS ignore

7

7

ns

SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1

fSCLK

SCLK frequency

20

25

MHz

tSCLKHIGH

SCLK high time

22

18

ns

tSCLKLOW

SCLK low time

22

18

ns

tSDIS

SDI setup

5

5

ns

tSDIH

SDI hold

10

10

ns

tCSS

CS to SCLK falling edge setup

32

20

ns

tCSH

SCLK falling edge to CS rising edge

10

10

ns

tCSHIGH

CS high time

15

15

ns

tSDODLY

SDO output delay from SCLK falling edge

3.5

45

3.5

32

ns

tSDODZ

SDO driven to tri-state

0

30

0

25

ns

tCSIGNORE

SCLK falling edge to CS ignore

7

7

ns

DIGITAL LOGIC

tRSTDLYPOR

POR reset delay

170

250

170

250

µs

tDACWAIT

Sequential DAC output updates

1

1

µs

tLDACS

LDAC setup

0

0

ns

tLDACH

LDAC hold

5

5

ns